A pulse width modulation signal receiving circuit
A pulse width modulation signal and pulse width signal technology, applied in the direction of logic circuit connection/interface layout, etc., can solve the problems of complex structure, large number of pins, large area, etc., to simplify the circuit structure, reduce chip area and power Power consumption, the effect of reducing the number of pins
Active Publication Date: 2017-03-15
SHAANXI BEIDOU HENGTONG INFORMATION TECH
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Problems solved by technology
Common inter-chip communication includes SPI and I 2 C interface circuits, but they require a large number of pins, complex structure, large area and high power consumption
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[0038] see figure 1 A pulse width modulation signal receiving circuit includes a pulse width signal receiving and controlling circuit 100 and a decoding circuit 200; the pulse width signal receiving and controlling circuit 100 is used to receive a pulse width signal and generate a control signal to control the decoding circuit 200 to work; The decoding circuit 200 converts the received pulse width signal into a digital signal for output.
[0039] The pulse width signal receiving and control circuit 100 includes: a first D flip-flop DFF1, a second D flip-flop DFF2, a third D flip-flop DFF3, a fourth D flip-flop DFF4, a fifth D flip-flop DFF5, a sixth D flip-flop Flip-flop DFF6, seventh D flip-flop DFF7, eighth D flip-flop DFF8, ninth D flip-flop DFF9, first AND gate AND1, first OR gate OR1, first NOR gate NOR1 and second NOR gate NOR2 .
[0040] The clock input terminal of the first D flip-flop DFF1 is connected to the clock signal input terminal CLK, the data input terminal ...
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The invention discloses a pulse width modulation signal receiving circuit. The pulse width modulation signal receiving circuit comprises a decoding circuit and a pulse width signal receiving and controlling circuit for receiving a pulse width signal and generating a signal for controlling the decoding circuit to work, wherein the decoding circuit is used for converting the received pulse width signal into a digital signal for outputting; the pulse width signal receiving and controlling circuit is used for receiving a pulse width modulation signal through a clock input port CLK and a data input port PWM, and outputting a clock gating signal LOG1-CLK, a reset control signal LOG2 and a latch clock signal LOG4; the decoding circuit is used for receiving a clock gating signal, a reset control signal and a latch clock signal, converting the pulse width signal into a binary digital signal, and outputting the binary digital signal through output ports D0, D1, D2, D3, D4 and D5; D5 is at a highest order; and D0 is at a lowest order. Through adoption of the pulse width modulation signal receiving circuit, the quantity of pins used in communication is reduced; the circuit structure is greatly simplified; the chip area is reduced; and the power consumption is lowered.
Description
technical field [0001] The invention relates to the technical field of mixed signal integrated circuits, in particular to a pulse width modulation signal receiving circuit. Background technique [0002] With the development of integrated circuit technology, higher and higher requirements are put forward for the high-speed interface of inter-chip communication. The interface circuit that needs to realize communication has as few pins as possible, simple structure, small area and low power consumption. Common inter-chip communication includes SPI and I 2 C interface circuits, but they require a large number of pins, complex structure, large area and high power consumption. Contents of the invention [0003] In order to solve the deficiencies of the prior art, the present invention proposes a pulse width modulation signal receiving circuit, which can realize high-speed communication between chips, and requires few pins, simple structure, small area and low power consumption....
Claims
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IPC IPC(8): H03K19/0175
Inventor 申向顺李波李卫斌王红丽姜恩春
Owner SHAANXI BEIDOU HENGTONG INFORMATION TECH