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Method for using interaction of server motherboard BMC and CPLD for rapid diagnosis of motherboard timing

A rapid diagnosis and server technology, applied in the detection of faulty computer hardware, functional testing, etc., can solve problems such as time-consuming, labor-intensive, and ineffective

Inactive Publication Date: 2015-02-25
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

It's time-consuming and labor-intensive, and it doesn't work very well

Method used

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  • Method for using interaction of server motherboard BMC and CPLD for rapid diagnosis of motherboard timing

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Embodiment Construction

[0017] In order to describe the implementation process of the present invention more clearly, with the above figure 1 The interactive topology diagram is used for narrative explanation. The left side of the picture is the management unit BMC on the server motherboard, and the right side is the CPLD (FPGA) on the motherboard that controls timing.

[0018] 1) On the mainboard of the server, the current time is when the mainboard is in STBY state (power on but not on), BMC and CPLD (FPGA) are both in working state; but there is no communication between the two. After starting up, the timing of the motherboard is under the control of CPLD (FPGA), and it starts up according to the predetermined timing; except for the necessary timing interaction, there is no communication between the two. Therefore, to use BMC and CPLD (FPGA) to judge whether the timing is normal, there are two necessary conditions

[0019] a), BMC and CPLD (FPGA) need a communication bus;

[0020] b) The STBY s...

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Abstract

The invention provides a method for using interaction of a server motherboard BMC (baseboard management controller) and CPLD (complex programmable logic device) for rapid diagnosis of motherboard timing and relates to the field of server equipment. Through the use of the characteristics of customizable pins and internal registers of CPLD (FPGA-field programmable gate array), a communication bus is externally added on an existing motherboard CPLD (FPGA) to be used for communicating with BMC, and CPLD (FPGA) is internally added to record a timing state of the motherboard. Monitor and record of the timing state of the motherboard are realized with no motherboard hardware to be added.

Description

technical field [0001] The invention relates to the field of server equipment, in particular to a method for quickly diagnosing the sequence of the main board by using the BMC and CPLD of the main board of the server. Background technique [0002] The complexity of the current server motherboard circuits is gradually increasing, and the timing of the motherboard is becoming more and more complicated. Therefore, it is particularly important to quickly diagnose timing problems. However, at present, when a timing problem occurs on the motherboard, engineers must use an oscilloscope to perform sequential measurements according to the timing diagram of the motherboard to find the root cause of the problem. This method is time-consuming and laborious. [0003] The timing of the server motherboard is basically controlled by CPLD (FPGA). Once the motherboard has a timing problem during startup, operation or shutdown, it will be a very difficult problem for engineers and customer se...

Claims

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Application Information

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IPC IPC(8): G06F11/26
Inventor 廖明超
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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