FPGA-based time division multiplexing cascaded integrator-comb decimation filter and realization method thereof

A cascaded integral comb and decimation filter technology, which is applied in impedance networks, digital technology networks, electrical components, etc., can solve the problem of consuming FPGA resources, reduce hardware resource occupation, increase computing speed, and improve structural efficiency. Effect

Active Publication Date: 2015-03-04
HUAQIAO UNIVERSITY
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Problems solved by technology

Although this implementation can make full use of the parallelism of the FPGA to improve the execution speed and sampling rate of the filter, it consumes twice as many FPGA resources.

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  • FPGA-based time division multiplexing cascaded integrator-comb decimation filter and realization method thereof
  • FPGA-based time division multiplexing cascaded integrator-comb decimation filter and realization method thereof
  • FPGA-based time division multiplexing cascaded integrator-comb decimation filter and realization method thereof

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Embodiment Construction

[0032] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0033] The present invention provides a method for realizing FPGA-based time-division multiplexing cascaded integral-comb decimation filtering, performing cascaded integral-comb filtering on the in-phase signal and the quadrature signal in a time-division multiplexing manner, specifically: the in-phase The signal and the orthogonal signal are time-division multiplexed and combined into one signal. After cascaded integral filtering, resampling is performed, and then filtered by a cascaded comb filter unit, and finally the output signal is demultiplexed into the processed synchronous The phase signal and the processed quadrature signal are two signals.

[0034] More specifically, the in-phase signal and the quadrature signal are alternately input into one input signal through a gate signal with the same frequency as the input signal sampling clo...

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Abstract

The invention discloses a time division multiplexing cascaded integrator-comb decimation filter, comprising a multi-phase clock generation, distribution and control module, a cascaded integrator filter using a time division multiplexing and pipeline accumulator, a sampling rate conversion module, a time division multiplexing and cascade comb filter module and an in-phase and quadrature (IQ) input signal multiplexing module. Compared with the traditional cascaded integrator-comb (CIC) filter structure, the FPGA-based time division multiplexing cascaded integrator-comb decimation filter takes full use of the features of the FPGA (Field Programmable Gate Array) structure; while the occupation of the internal hardware resource of the FPGA chip is reduced, the computing speed of a circuit can be maintained or even improved, so that the efficiency of the cascaded integrator-comb (CIC) filter structure widely applied to digital communication systems and realized on the basis of the FPGA is improved.

Description

technical field [0001] The present invention relates to a kind of cascaded integral comb filter, more specifically, relate to a kind of FPGA-based time-division multiplexing cascaded integral-comb decimation filter, and an FPGA-based time-division multiplexing cascaded integral comb filter decimation filtering method. Background technique [0002] With the emergence of high-speed analog-to-digital, digital-to-analog conversion chips, large-scale digital integrated circuits and FPGA chips, digital filtering technology is widely used in communication systems. High-speed digital filters can generally be implemented with dedicated DSP chips, such as Texas Instruments TMS320 series, or FPGA chips, such as XILINX's SPARTAN series and ALTERA's CYLONE series. The latter has the characteristics of flexible design and parallel high-speed operation, and is increasingly used to realize different digital filters. [0003] Since in modern communication systems, the frequency of the inte...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03H17/02
Inventor 黄锐敏朱述伟凌朝东李国刚
Owner HUAQIAO UNIVERSITY
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