236 results about "CICS" patented technology

An earpiece auditory device includes a behind-the-ear (BTE) component, which includes processing circuitry. In an embodiment, the device also includes a completely-in-canal (CIC) component, shaped to fit into the ear canal of the user such that it touches the bony portion of the ear canal. In some embodiments, the CIC component includes either a universal fit or a custom fit ear mold. The custom fit ear mold can be fabricated using a rapid prototyping technology, in which the contours of the user's ear canal are scanned, and the scan data is used either directly or indirectly to replicate the ear canal contours of that user into the custom fit ear mold. In some embodiments, the ear mold is detachably interconnected with a speaker module, preferably using either an intermediate sleeve or a detachable locking pin assembly. In another embodiment, the speaker module is permanently encapsulated within the ear mold.

In representative embodiments, the present invention is directed to an at least partially in-the-canal module. The module may include a speaker module that generates audio signals from an electrical driving signal. The speaker module has a tubular body with a diameter that is smaller than the ear canal of the user. The speaker module also includes an arcuate raised ridge. A cushion tip of deformable material may be used to enclose the speaker module within a tubular portion that applies an elastic force to the arcuate raised ridge to prevent removal of the speaker from the cushion tip. Also, the tubular portion is longer than the speaker module to cause the cushion tip to deflect during navigation through the canal. Further, the tip portion of the cushion tip possesses sufficient structural rigidity to prevent the speaker from being pushed through the cushion tip during navigation through the canal.

An interchangeable hearing aid control panel with at least one activation zone arranged in connection with a layered structure. The layered structure has an electrically non-conducting substrate, an electrically conducting path arranged in connection with the substrate, and an electrically conducting member, such as a conducting foil, arranged at a predetermined distance from the activation zone. The activation zone can be either in a deactuated or in an actuated state. In the actuated state the conducting member and the conducting path are electrically connected while disconnected in the deactuated state. Electrical connection to an associated hearing aid is by means of a connector, such as a plug, enabling the control panel to be easily changed. Preferably, the connector is formed by a piece of flexprint. The layered structure may comprise a second conducting path. In preferred embodiments activation zones are indicated by “poppel domes” formed by a surface layer covering the layered structure. The activation zones may form an MTO control or a volume control. To fit BTE hearing aids, the layered structure preferably has an elongated structure with a length of 1-4 cm. Other shapes can be formed to fit ITE, ITC and CIC hearing aids. In preferred embodiments, the control panel comprises one or more Silicon-based microphones protected behind a surface layer of the control panel.

According to the invention, a hearing instrument comprising at least one inner microphone operable to determine a sensing signal representative of an acoustic signal at a position in front of the user's eardrum—which may be an acoustic signal at a position between an ITE (or ITC or CIC) hearing instrument and the eardrum or between an earpiece and the eardrum—is used. In accordance with the invention, in front of the eardrum an acoustic signal is produced. The inner microphone creates a sensing signal representative of the acoustic signal, and the signal processing unit of the hearing instrument determines a characteristic of the user's ear canal based thereon and memorizes values indicative of the characteristic. According to a preferred embodiment, the characteristic is an acoustic coupling transfer characteristic, which is determined based on a comparison of a signal representative of the output signal of the signal processing unit's digital signal processing stage and the sensing signal. In contrast to the state of the art, no control loop is necessary to adapt the gain to the ear canal characteristic, but the memorized values may be used therefor.

The present invention is directed to a system for for automated interface generation for computer programs operating in different environments. The system comprises a utility which imports a CICS COBOL transaction source file, parses the communication area of the CICS file, and generates modelling information. The modelling information represents the nature and structure of data in the CICS transaction source file, and is written to a persistent data store. The utility uses the information in the persistent data store to generate an application programming interface. The application programming interface takes the data values from the other language and translates them to a formatted CICS COBOL communications area. This format is derived from the definition of the CICS communications area contained in the imported CICS program. After the translation runs, the resulting CICS COBOL communications area is translated back to the data values of the other language. This translation step also handles the data conversion between different codepages and machine architectures and program semantics. The resulting language values represent the result of the transaction. The CICS transaction is accessed using the CICS External Call Interface mechanism.

A method, apparatus, and article of manufacture for accessing a hierarchical database. An objects framework models the database as one or more objects. An Internet-enabled generic application program accesses the database via the objects framework. The present invention introduces an Internet-enabled generic application program for accessing hierarchical databases, such as an IMS TM database, by modeling the database into an objects framework and then accessing the database via the objects framework using standard tools, such as the DL/I TM query language for the IMS TM database. The Internet-enabled generic application program dynamically builds a DL/I TM query string based on web browser inputs. The generic application program loads the objects framework to instantiate IMS TM objects and dynamically constructs DL/I TM calls to access the IMS TM database. The generic application program can be used in a number of different environments, such as: (1) DL/I TM batch processing and (2) on-line transactions including both IMS TM and CICS TM transactions. Moreover, the generic application program and objects framework can be executed in any MVS address space, including IMS TM and non-IMS TM address spaces, such as web server address spaces. With this invention, customers can continue to access their business data in IMS TM databases using the latest Internet technology, without relying on legacy application programs and without developing new application programs. Thus, the present invention offers improved IMS TM application programming productivity by supporting IMS TM business objects and data objects, by eliminating complicated DL/I TM programming, and by supporting use of object-oriented programming tools.

A pipelined analog-to-digital converter (ADC) is calibrated to enable production of an n-bit digital output representing an n-2 bit binary word, where "n" is a selected large positive integer, for example without limitation on the order of ten (10). In an analog-to-digital converter (ADC) having a plurality stages, each stage includes a stage input connection, a stage output connection, and a capacitor circuit including first and second predetermined capacitors (C1 and C2) and a variable capacitance calibration capacitor (Ccal). The first and second capacitors and the variable capacitance calibration capacitor are connected to each other at a capacitor common node. An amplifier input connection is connected to a capacitor common node. A comparator input connection (CIC) is connected to a stage input connection. A track and hold circuit (THC) is coupled to an amplifier output connection, and a source follower circuit (SF) is connected to a stage output connection.

Novel techniques for operating a transactional processing system on which a CICS progran is stored. The CICS program includes logic for implementing business rules, and logic for accessing data. An ODBC invocation proven, stored on a client data processing system, is adapted to invoke stored procedures. The invocation program, executed by a remote computer, causes execution of the stored CICS program at the transactional processing system. The invocation program causes the CICS program to access data from a computer-readable data storage medium, and to filter the data by implementing business rules. The transactional processing system is equipped with business rules. The trnnsactional processing system is equipped with stored procedures (queries), executed in response to a query command stored in the invocation program and issued by the client data processing system. Thus, the result of the query include accessed data to which business rules have been applied. The results can be processed by stored client programs.

The invention discloses a digital signal down-conversion processing system based on an MIMO real-time testing platform, pertaining to the technical field of digital signal processing. The system comprises four DDC modules and each DDC module consists of four independent digital signal down-conversion processing channels. Each channel consists of an analog-to-digital converter, a digital quarter mixer and a digital decimation filter set. The digital quarter mixer consists of a digital controlled oscillator and two paths of multipliers, and the digital controlled oscillator is respectively connected with the two multipliers; the digital decimation filter set consists of two groups of filters with complete same parameters and each filter group respectively comprises a CIC decimation filter, a CFIR compensation filter and a PFIR matched filter which are connected in sequence. The system has good expansibility and modularization and can meet the requirements of real-time and high-speed performance.

The invention provides a multisystem signal simulation device comprising a baseband signal generation module and a signal conditioning module. The baseband signal generation module comprises two parts of a digital circuit and an analog circuit. The analog circuit part comprises an analog clock circuit and a digital-to-analog conversion circuit. The digital circuit part comprises a clock management module, a data generation module, a digital modulation module, an FIR formation filtering module, a CIC interpolation module and an amplitude and phase calibration module. The signal conditioning module comprises an orthogonal modulation module, a broadband frequency conversion module, an amplitude control module and an amplification attenuation module. A baseband orthogonal modulation signal is realized in the internal part of an FPGA so that degree of complexity of the baseband signal design in the FPGA can be reduced, the requirement for DAC sampling rate and data width can be reduced and high-index output of a carrier modulation signal can be realized. A radio frequency PIN amplitude control technology is adopted so that small step and high dynamic range of signal amplitude can be realized.

A cascaded sigma-delta modulator has several modulator loops that have one or two sets of integrators, summers, and scalers, and a quantizer that generates a loop output. Input muxes to each loop select either an overall input or the loop output from a prior loop, allowing the modulator loops to be cascaded in series or to operate separately. Filter-configuring muxes after each modulator loop select either that loop's output or a loop output from any prior loop, or a zero. Each filter-configuring mux drives an input to a modified CIC filter. The modified CIC filter has an initial delay stage that receives the first filter-configuring mux output, and successive integrator stages that each receives a successive filter-configuring mux output. The modified CIC filter is a combination of a digital transform filter and a Cascaded-Integrator-Comb (CIC) filter. Modulator loops are powered down for lower-performance configurations or cascaded together for higher-performance configurations.

The invention discloses a digital filter, a collocation method of the digital filter, an electronic device and a wireless communication system. The digital filter comprises a set of cascade integrator comb (CIC) filter group. The collocation method of the digital filter comprises that signals are selected through working modes received by the digital filter, a filter rate configuration value which is stored in a register and corresponds to each working mode is selected, a working clock is confirmed according to a main clock selection signal and a clock frequency dividing ratio selection signal in the filter rate configuration value, each filter can be switched in the different working modes according to the confirmed working clock, the digital filter is configured according to the different working modes, and accordingly the purpose that on the basic that the filter needs not to be re-designed, the different working modes are selected flexibly is achieved. The material waste is avoided when a clock generation circuit and the filter are re-designed in the process of the conversion of the working modes, and accordingly the purposes that cost is reduced and expandability is improved are achieved.

An apparatus for demodulating a digital input signal having a pre-assigned symbol rate by using a single sample clock signal is disclosed. The pre-assigned symbol rate is selected from the group consisting of a plurality of symbol rates. The apparatus comprises: a Cascaded Integrated Comb (CIC) Decimator filter configured to perform a filtering-decimation operation to isolate the down converted digital signal having the pre-assigned symbol rate; a Shaper configured to restore an original spectrum of the I and Q components of the CIC output signal; and a CIC tuner loop filter configured to insert the estimated by the Coarse Frequency estimation block frequency offset into a carrier loop in order to complete a carrier recovery of the pre-assigned input digital signal.

An automated system provides automated manufacturing of photovoltaic standard power modules for utilization in a space solar array, in both rolled blanket and z-folded configurations. The automated system provides robotically controlled systems for CIC-ing, glassing, stringing, laydown and acceptance testing of interconnected photovoltaic devices. A method of manufacturing the photovoltaic standard power modules includes the steps of robotic positioning of diodes, interconnects and busbars onto a SPM stringing tray followed by the robotic positioning of bare cells into position adjacent to the diodes, interconnects and busbars to form strings. The SPM stringing tray is thereafter robotically positioned adjacent to an integral welder for welding of the front side of the string. Cover glass is thereafter robotically placed over the cells. The string is flipped and the backside of the string is robotically positioned for welding.

The embodiment of the invention provides a design method for a cascade filter, which comprises the following steps of: determining the interpolation times N of the filter; calculating the filter coefficient of a programmable finite impulse response (PFIR) filter, and obtaining a design scheme of a cascade combined filter of PFIR and cascaded integrator comb (CIC) filters; and when the interpolation times of the cascade combined filter of the PFIR and CIC filters does not reach the predetermined times, designing a half band (HB) filter, so that the filter performance of the cascade combined filter of the PFIR and CIC filters and the HB filter meets the interpolation times requirement of a system, and the design of the PFIR filter is realized by adopting a multistage design scheme. According to the embodiment provided by the invention, by adopting the design device for the multistage filter, the order of the designed filter is in a realizable range of the FPGA, and the indexes such as interpolation times of signals, error vector magnitude (EVM), adjacent channel power ratio (ACPR) and the like can meet the protocol requirement. Moreover, according to the technical scheme provided bythe invention, the resource consumption of the filter is also lower than that of the design method for the traditional filter, and the use of FPGA hardware resources can be effectively reduced.

The invention provides a method for adjusting a time domain parallel sampling rate, which is applicable to the technical field of digital information transmission. The method is characterized in that all the treatments adopt parallel algorithms and large-scale digital sampling rate conversion is realized by combining a CIC filter, a CFIR filter, a PFIR filter and a fractional space decimation filter; wherein the CIC decimation filter is realized by adopting a time domain parallel structure and the CFIR filter and the PFIR filter adopt a time domain parallel structure based on a multiphase filter. The fractional space withdrawal device consists of a controller and a polynomial interpolator; the controller accelerates the processing speed during the hardware realization by adopting a method that all the parallel branches are mutually independent; the polynomial interpolator is realized by look-up and saves the limited logic and multiplier unit resources in a programmable logic device. The system is applicable to the realization of full-digital circuits, especially the realization of a field-programmable gate array (FPGA).

The invention discloses a method for processing a broadband receiving digital front end, which comprises the following steps that: 1, received radio frequency signals are divided into n paths of signals, and each path of the signals is subjected to frequency mixing respectively, and the difference of the frequencies of the frequency mixing among the paths is 80 MHz, then the paths of signals are processed respectively and are transmitted to an AD (Analogue-Digital Converter) for sampling with the sampling frequency of F1, and digital medium frequency signals with the centre frequency of F2 and the bandwidth of 80MHz are generated by each path, and are transmitted to a FPGA (Field Programmable Gata Array) for processing; 2: a corresponding AD is selected to input signals according to a current signal frequency code of the system, a DDS (Digital Display Scope) is controlled to generate orthogonal digital local oscillation consistent with a signal frequency spectrum sampled by the AD, the signals input by the AD are multiplied by the orthogonal digital local oscillation generated by the DDS respectively and the frequency spectrum is shifted to a zero intermediate frequency to carry out orthogonal decomposition to acquire an I path of baseband signals and a Q path of baseband signals which are orthogonal to each other; and 3: the velocity of a signal data stream acquired after theshift of the frequency spectrum is F1, the signals are subjected to extraction filtering for M times by using a CIC extraction filter to acquire an I baseband signal and a Q baseband signal with the velocity of F1/M, and the baseband signals are subjected to complementary filtering respectively by using an FIR low-pass filter.

A multi-mode digital down-converter for down-converting an incoming IF signal to baseband according to a selected air interface standard. The down-converter comprises a re-configurable gain control block controlled by a first gain parameter for amplifying the incoming IF signal and a mixer stage for down-converting the amplified incoming IF signal to produce a first in-phase baseband signal. The down-converter further comprises a reconfigurable CIC decimation filter block controlled by a second gain parameter and a first decimation parameter. The reconfigurable CIC decimation filter block filters the first in-phase baseband signal according to the second gain parameter and decimates the first in-phase baseband signal according to the first decimation parameter. The first and second gain parameters and the first decimation parameter are determined by the selected air interface standard.