Digital filter, collocation method of digital filter, electronic device and wireless communication system
A digital filter and filter technology, applied in digital technology networks, electrical components, impedance networks, etc., can solve the problems of poor scalability and high cost, and achieve the effects of avoiding material waste, reducing costs, and improving scalability.
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Embodiment 1
[0084] Such as Figure 4 As shown, it is a schematic structural diagram of a digital filter disclosed by an embodiment of the present invention, which mainly includes: a register set 1 , a clock generation circuit 2 and a filter set 3 . Figure 4 The dotted arrows in the middle indicate clock paths, and the solid arrows indicate data paths.
[0085] The register group 1 is used to pre-store the filter rate configuration values corresponding to each working mode, and when receiving the mode selection signal, select the filter rate configuration value corresponding to the current working mode according to the mode selection signal.
[0086] Such as Figure 4 As shown, in this embodiment of the present invention, when the working mode selection signal A is received, the filter rate configuration value corresponding to the current working mode is selected in the list of the register group 1 according to the working mode selection signal A, and output to Clock generation circui...
Embodiment 2
[0099] Based on the above-mentioned digital filter disclosed in Embodiment 1 of the present invention, the basic implementation principles of the CIC filter and the FIR filter are as follows.
[0100] The internal implementation structure of the FIR filter is as follows Figure 5 shown. It mainly includes: n+1 delay units D, n multiplication units F and an addition unit H corresponding to the delay units D. Figure 5 The dotted arrows in the middle indicate clock paths, and the solid arrows indicate data paths.
[0101] The process of realizing data down-sampling and filtering is: filtering data on a high-frequency clock, and then down-sampling to a low-frequency clock. Based on attached Figure 5 , where a1, a2, a3, ..., an are n coefficients of the FIR filter, n is the order of the FIR filter; data_f_high is the data from the high-frequency clock; data_f_low is the low-frequency data after downsampling; clk_f_high Is a high-frequency clock; clk_f_low is a low-frequency c...
Embodiment 3
[0140] Based on the structure of the digital filter shown in Embodiment 1 and Embodiment 2 of the above-mentioned present invention, Embodiment 3 of the present invention also discloses a corresponding digital filter configuration method, as shown in Figure 9 As shown, it is a flowchart of a configuration method of a digital filter disclosed in Embodiment 3 of the present invention, which mainly includes the following steps:
[0141] Step S101, receiving a working mode selection signal.
[0142] Step S102, according to the working mode selection signal, select the filter rate configuration value corresponding to the current working mode in the register set, and the filter rate configuration value corresponding to each working mode is pre-stored in the register set.
[0143] During the execution of step S101 and step S102, the configuration of the digital filter is based on the working mode selection signal received by the digital filter. Specifically, the digital filter sele...
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