Sampling time error correction method for multi-channel parallel analog-digital converter (ADC) system

A sampling time and error correction technology, applied in the direction of analog/digital conversion calibration/testing, etc., can solve the problems of limiting the application range of the input signal bandwidth, and achieve the effect of reducing the design difficulty and eliminating the aliasing problem.

Active Publication Date: 2015-03-04
DATANG MICROELECTRONICS TECH CO LTD
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Problems solved by technology

However, this cannot avoid the problem of aliasing, which greatly l

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  • Sampling time error correction method for multi-channel parallel analog-digital converter (ADC) system
  • Sampling time error correction method for multi-channel parallel analog-digital converter (ADC) system
  • Sampling time error correction method for multi-channel parallel analog-digital converter (ADC) system

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Embodiment Construction

[0025] The present invention is based on the frequency domain relationship between the output signal of the multi-channel parallel ADC system and the analog input signal, based on the switch circuit and the analog low-pass filter, and proposes a method to correct the multi-channel by eliminating the system error signal in the output signal Methods for Sampling Time Error in Parallel ADC Systems. Since the solution of the systematic error needs to know the value of the sampling time error, the whole correction method mainly includes two parts: the estimation of the sampling time error and the solution of the systematic error.

[0026] like figure 1 As shown, the analog input signal x(t) is divided into two paths through the switch circuit. When the switch circuit is connected to paths 1 and 3, paths 1 and 3 are connected, at this time, the analog input signal x(t) is filtered through an analog low-pass filter to obtain an analog signal d(t), and the analog signal d(t ) to obt...

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Abstract

The invention discloses a sampling time error correction method for a multi-channel parallel ADC system. The method comprises the steps that the output end of an analog low-pass filter and the input end of the multi-channel parallel ADC system are connected through a switching circuit, and an analog input signal x (t) enters the analog low-pass filter to obtain a narrow-band analog signal d (t), the multi-channel parallel ADC system samples the d (t) to obtain a multi-channel sampling output signal yd (n), and LMS-frequency domain self-adaption estimation is performed on the yd (n) to obtain a sampling time error omega (n); sending the analog input signal x (t) into the multi-channel parallel ADC system through the switching circuit, performing sampling to obtain a sampling output signal y (n) which is processed by a digital differential analyzer and then subjected to a first multiplying unit with omega (n) to obtain a system error signal c (n), and y (n) and c (n) are subjected to a subtractor to obtain the corrected output signal yc (n). According to the method, the problems of aliasing and the difficulty in achieving of high-rate hardware circuits are solved on the basis of error correction.

Description

technical field [0001] The invention relates to the field of high-speed and high-precision analog-to-digital conversion, in particular to a sampling time error correction method for a multi-channel parallel ADC system. Background technique [0002] Analog-to-digital converter (ADC), as the interface between analog technology and digital technology, is widely used in modern electronic systems. With the development of digital signal processing technology, digital circuits have higher and higher requirements on the sampling rate of analog-to-digital converters. The most important performance parameters of an ADC are conversion accuracy and conversion speed. Limited by the current level of ADC chip development, it is difficult for a single ADC to have high speed and high precision at the same time. The speed and precision of ADC are mutually restricted. With the increase of ADC conversion speed, its precision tends to decline. The constraint between the two has become the main...

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Application Information

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IPC IPC(8): H03M1/10
Inventor 齐佩佩高洪福
Owner DATANG MICROELECTRONICS TECH CO LTD
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