A Diversity Multi-chip Synchronization System
A synchronous system and multi-chip technology, applied in general control systems, control/adjustment systems, instruments, etc., can solve the problems of different clock timings of multiple groups of chips, and the inability of multiple groups of chips to work synchronously, so as to achieve the effect of improving reliability
Active Publication Date: 2017-02-15
NO 24 RES INST OF CETC
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like figure 1 As shown, taking four frequency division as an example, when multiple groups of chips are used at the same time, the initial state of the frequency divider inside the chip is different, which will lead to different internal clock timings of multiple groups of chips, making it impossible for multiple groups of chips to work synchronously
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[0042] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0043] The sending end and the receiving end of a kind of diversity multi-chip synchronous system embodied in the present invention are respectively as follows Figure 4 , Figure 5 shown. The specific structure, connection relationship, and functional relationship are the same as the content of the invention in this specification, and will not be repeated here.
[0044] The specific implementation manners of the present invention are not limited to the following description, and are now further described in conjunction with the accompanying drawings.
[0045] The structural diagram of the sending end of the diversity multi-chip synchronization system implemented in the present invention is as follows Figure 4 shown. exist Figure 4 middle:
[0046] The function of the driver 1 and the driver 2 is to increase the drivin...
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The invention relates to a diversity type multichip synchronization system, and belongs the technical field of high-speed DDS and high-speed DAC multichip application. Compared with common multichip synchronization systems, the diversity type multichip synchronization system has the following characteristics that 1) two paths of synchronization signals sync1 and sync 2 are transmitted at a transmitting end, the two paths of signals can act as standby signals for each other, and the other can still transmit synchronization information when one receives external interference; 2) receiving clocks with appropriate time sequences of the signal sync1 and the signal sync 2 are given at a receiving end via a mode of traversal searching of N paths of clock signals so that receiving reliability is enhanced; and 3) correctness of receiving of the two paths of the synchronization signals is monitored by using a receiving state monitor, and when receiving of one path is incorrect, the other path with correct receiving can be used via switching. Synchronization reset signal receiving reliability can be substantially enhanced by the diversity type realization method. The circuit can be widely applied to realization of a high-speed DDS and high-speed DAC multichip synchronization function.
Description
technical field [0001] The invention belongs to the technical field of multi-chip application in high-speed DDS and high-speed DAC, and relates to a diversity multi-chip synchronous system. Background technique [0002] High-speed DDS and DAC chips need to use multiple sets of clock signals with different frequencies, generally the 2 clock signals with the highest frequency N frequency division generated. Such as figure 1 As shown, taking the frequency division by four as an example, when multiple sets of chips are used at the same time, the initial state of the frequency divider inside the chip is different, which will lead to different clock timings inside the multiple sets of chips, making the multiple sets of chips unable to work synchronously. [0003] Conventional multi-chip synchronous design timing such as figure 2 As shown, taking four frequency division as an example, the master synchronous chip outputs a synchronous reset signal (generally the maximum frequenc...
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IPC IPC(8): G05B19/042
CPCG05B19/042
Inventor 张俊安张瑞涛刘军付东兵杨毓军魏亚峰李广军
Owner NO 24 RES INST OF CETC