Method of parallel opc on layout

Abstract

The invention discloses a method for performing parallel OPC (Optical Proximity Correction) on a layout. The method comprises the following steps: extracting a minimum bounding rectangle of each module in the layout; selecting four vertexes of the layout as the centers of four initialization blocks respectively; calculating the distance from each module to the center of each initialization block and assigning each module to the initialization block with the smallest distance respectively; calculating the center of each middle block according to the position of each module included by each middle block; calculating the distance from each module to the center of each middle block and assigning each module to the middle block with the smallest distance respectively; repeating the steps 4 and 5 until the center of the middle block is not changed to obtain four final blocks; performing the OPC on the four final blocks of the layout respectively; combining the OPC results of the four final blocks of the layout. According to the method, the speed for processing large-scale physical layout data can be greatly improved and the processing time is reduced.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing process method, in particular to a method for performing parallel OPC on a layout. Background technique [0002] As the design rules become smaller and smaller, some auxiliary technologies have also emerged. Currently, one of the most important steps below the 0.18μm process is optical proximity correction (OPC). In the process below 0.18μm, if the pattern of the layout is not corrected, the image on the wafer (wafer) will be distorted (distort), so OPC can make the image etched on the wafer closer to the shape of the layout. as shown in the picture figure 1 As shown, it is a schematic diagram of the role of OPC in the photolithography process; the layout 102 is obtained after OPC is performed on the layout 101 of the design, and the edge of the layout 102 is corrected and different from the layout 101; the mask (Mask) is made through the layout 102 103, the shape of the photom...

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Problems solved by technology

Depend on figure 1 It can be seen from the above that if no OPC correction is performed, the obtained photoresist pattern 104 will be quite different from the designed layout 101

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