High voltage electrostatic protection structure

Abstract

The invention discloses a high-voltage electrostatic protection structure which includes an N-type LDMOS which is arranged in a P-type burial layer on a silicon substrate; a polysilicon gate right-side active region which is an LDMOS drain region and includes a high-voltage N well arranged on the right side of the P-type burial layer and a first N+ diffusion region, wherein a field oxide region is arranged between the first N+ diffusion region and a polysilicon gate, and both of the first N+ diffusion region and the field oxide region are surrounded by the high-voltage N well; and a polysilicon gate left-side active region which is an LDMOS source region and includes a high-voltage P well arranged on the left side of the P-type burial layer and an N well. Part of a second N+ diffusion region and a first P+ diffusion region are on the N well and the remaining part of the second N+ diffusion region is on the high-voltage P well. A second P+ diffusion region is on the high-voltage P well. Oxide regions are arranged among the first P+ diffusion region, the second P+ diffusion region, and the second N+ diffusion region. The first P+ diffusion region, the second P+ diffusion region and the polysilicon gate are lead out and grounded. The first N+ diffusion region is lead out and used as an electrostatic input end. The invention provides the high-voltage electrostatic protection structure which is unlikely to trigger a latch-up effect.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a high-voltage electrostatic protection structure. Background technique [0002] Electrostatic discharge (ESD) damage to electronic products has always been a problem that is not easy to solve. For high-voltage processes, electrostatic protection devices not only need to meet the requirement that the withstand voltage be greater than the power supply voltage, but also need to be less than the damage of the protected device. Voltage is fine. Such as figure 1 As shown, the high-voltage NLDMOS structure usually used for electrostatic protection is under the occurrence of static electricity. After the ESD positive charge enters the drain region of the structure from the input and output pads, the potential of the N-diffusion region is raised, and an avalanche breakdown occurs, and the breakdown current passes through The P+ diffusion region in the P well is drawn out...

AI Technical Summary

Problems solved by technology

The parasitic triode is turned on mainly by the junction breakdown between the N-diffusion region and the high-voltage P well to trigger the parasitic NPN to turn on. The snapback voltage is very low, and it is not easy to adjust, and it is easy to trigger the latch-up effect.

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