An exception handling method and its processing structure that tolerates cache loss and quickly clears the pipeline

Abstract

An exception processing method and its processing structure that tolerates the lack of cache and quickly clears the pipeline. The processing method includes: firstly defining the "false hit" state, identifying the access result of the invalid instruction cleared by the pipeline to the cache; in the "false hit" state, the cache The correctness of the instruction code or data word is not guaranteed, and the cache information corresponding to the access address is directly output; in the "false hit" state, the pipeline clearing signal is directly applied to the instruction cache during the instruction fetch operation in the "false hit" state, so that the "false hit" state is selected when the invalid instruction accesses the cache ; At the beginning of exception processing, use the "or" logic selection of the pipeline clear signal and the memory access level invalid flag signal to control the data cache; when an exception occurs, the cache enters the "false hit" state to make the pipeline continue to advance. The invention also discloses the structure applying the exception handling method. The invention can speed up the exception processing speed and improve the real-time performance of the system.

Description

technical field [0001] The invention relates to a structure and a method for a RISC processor of a Harvard structure to quickly clear a pipeline when performing abnormal processing, in particular to an abnormal processing method and a processing structure for quickly clearing a pipeline that tolerates a lack of cache. Background technique [0002] At present, high-performance microprocessors generally use a hierarchical multi-level cache as a buffer for data and instructions, so as to reduce the speed difference between the processor and the memory. Among them, the first-level cache has a small access delay, which is basically consistent with the speed of the processor. In order to obtain parallel access to instructions and data, it is usually divided into independent instruction cache and data cache, which is the so-called Harvard structure; The second-level cache generally stores instructions and data together, and it can be on-chip or off-chip; in future high-end designs,...

AI Technical Summary

Problems solved by technology

[0005] Aiming at the problems in the prior art, the present invention provides a method to eliminate the pipeline stall caused by the lack of cache access of invalid instructions by setting the "false hit" state in the conventional blocking cache, without adding additional complex hardware logic That is, it can quickly empty the pipeline in occasional abnormal events, thereby speeding up the speed of exception processing and improving the real-time tolerance of the computer system. The exception handling method and its processing structure of quickly emptying the pipeline due to lack of cache

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