Semiconductor testing structure
A technology for testing structures and semiconductors, which is applied in the testing of single semiconductor devices, semiconductor devices, semiconductor/solid-state device components, etc., can solve the problem of low wafer utilization, and achieve accurate test results.
Active Publication Date: 2015-03-25
SEMICON MFG INT (SHANGHAI) CORP
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Problems solved by technology
However, one test structure can only test 8 MOS transistors, and can only obtain 8 sets of data, and the chip utilization rate is not high
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[0021] Because the existing test structure usually utilizes the test pad to test the component to be tested, and the chip area occupied by the test pad is often larger than the chip area of a component, especially when the component to be tested is a MOS transistor, The size of the current MOS transistors is usually at the nanometer level, and the size of the test pads is usually at the micron or even millimeter level. Therefore, the number and size of the test pads determine the wafer area occupied by the entire test structure. Even if the number of MOS transistors to be tested is far greater than 8, the wafer area occupied by the test structure will not change greatly, so it is necessary to increase the number of MOS transistors to be tested as much as possible without increasing the number of test pads. The number of MOS transistors, so that more test data can be obtained.
[0022] For this reason, the present invention provides a kind of semiconductor testing structure, ...
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A semiconductor testing structure comprises a substrate, a plurality of MOS transistors and a plurality of test bonding pads, wherein the MOS transistors and the test bonding pads are located on the substrate. First electrodes, second electrodes and third electrodes of the MOS transistors are electrically connected with the test bonding pads, at least one test bonding pad is electrically connected with the first electrode, the second electrode or the third electrode of one MOS transistor, and at most one of the test bonding pad electrically connected with the first electrode, the second electrode or the third electrode of one MOS transistor or other test bonding pads electrically connected with the first electrode, the second electrode or the third electrode of any one MOS transistor is shared. By means of the semiconductor testing structure, the number of the MOS transistors to be tested can be remarkably increased under the condition that the test bonding pads are not increased, accordingly improvement of wafer utilization rate is facilitated, and a test result is accurate.
Description
technical field [0001] The invention relates to the field of semiconductor testing, in particular to a semiconductor testing structure. Background technique [0002] In an integrated circuit system, circuit designers sometimes need to do a detailed analysis of the current-voltage relationship of some circuits in the system. At this time, it is necessary to do transistor-level simulation and establish component models. The transistor-level simulation usually tests the current-voltage relationship of the most basic components such as a single MOS transistor, so as to provide data support for transistor-level simulation and component model establishment. [0003] In order to accurately establish the model of components, it is hoped that the more data that can be measured, the better. Therefore, it is hoped that the number of components that can be measured in one test module is as large as possible. However, since the chip area of the test structure used to test the current-...
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IPC IPC(8): H01L23/544G01R31/26
Inventor 甘正浩冯军宏
Owner SEMICON MFG INT (SHANGHAI) CORP