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High-speed digital noise source

A technology of digital noise and noise source, applied in the field of high-speed digital noise source generation, can solve the problems of low output rate and high power consumption, and achieve the effect of controlling power consumption and preventing function failure

Inactive Publication Date: 2015-03-25
QUANTUMCTEK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The present invention proposes a high-speed digital noise source, which can solve the problems of large power consumption and low output rate of FPGA-based high-speed digital noise sources

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0015] The high-speed digital noise source used in this embodiment is realized based on FPGA, and an oscillator is used to output a high-frequency, large-jitter clock signal, and then a low-frequency pure clock is used to sample it, and finally the obtained signal is output.

[0016] The power consumption of the noise source is mainly determined by the high frequency and large jitter clock signal, and the generation of the high frequency and large jitter clock signal is based on a loop formed by an odd number of NOT gates. Wherein, in order to control the dynamic power consumption of the noise source, the noise source adds a switch signal for controlling the closing and opening of the loop.

[0017] The noise source is realized by sampling a high-frequency, large-jitter clock signal with a low-frequency pure clock, and the central oscillation frequency of the high-frequency, large-jitter clock signal is particularly critical here. If it is too low, it may lead to a decrease in...

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Abstract

The invention provides a high-speed digital noise source which is obtained on the basis of an FPGA. A signal obtained by outputting a high-frequency and large-shake clock signal through an oscillator and then sampling the generated high-frequency and large-shake clock signal through a low-frequency purified clock signal is the final required noise source. The high-frequency and large-shake signal is generated on the basis of a loop composed of an odd number of not gates; meanwhile, a switching signal used for controlling the loop to be closed and opened exists, and the central oscillation frequency of the switching signal ranges from 1.5 GHz to 3 GHz. The invention further provides the redundant design of the high-speed digital noise source. The high-speed digital noise source has the advantages that the problems that a digital noise source based on the FPGA is high in power consumption and low in output rate are solved, the power consumption of the noise source is effectively controlled, the requirement for the output rate is met, and the FPGA can be prevented from large damage.

Description

technical field [0001] The invention relates to generation of a noise source, and in particular provides a method for generating a high-speed digital noise source based on FPGA. Background technique [0002] In the existing technical solutions for generating noise sources, the high-frequency noise source based on field programmable gate array (FPGA) generally uses an oscillator to output a high-frequency clock signal, and then uses a lower-frequency pure clock to process it. Samples are digitized and output. The generated high-speed digital noise source can be used to generate random numbers, and has many applications in secure communication, information security, cryptography and other fields. [0003] Among them, oscillators used to generate high-frequency clock signals are usually divided into differential oscillators and single-ended oscillators, and different oscillators have different sensitivity to different noise sources. Differential oscillators are less sensitive...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03B29/00
Inventor 不公告发明人
Owner QUANTUMCTEK
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