High-speed digital noise source
A technology of digital noise and noise source, applied in the field of high-speed digital noise source generation, can solve the problems of low output rate and high power consumption, and achieve the effect of controlling power consumption and preventing function failure
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[0015] The high-speed digital noise source used in this embodiment is realized based on FPGA, and an oscillator is used to output a high-frequency, large-jitter clock signal, and then a low-frequency pure clock is used to sample it, and finally the obtained signal is output.
[0016] The power consumption of the noise source is mainly determined by the high frequency and large jitter clock signal, and the generation of the high frequency and large jitter clock signal is based on a loop formed by an odd number of NOT gates. Wherein, in order to control the dynamic power consumption of the noise source, the noise source adds a switch signal for controlling the closing and opening of the loop.
[0017] The noise source is realized by sampling a high-frequency, large-jitter clock signal with a low-frequency pure clock, and the central oscillation frequency of the high-frequency, large-jitter clock signal is particularly critical here. If it is too low, it may lead to a decrease in...
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