Distributive control and double-clock asynchronous sending and receiving module and FIFO (First In First Out) device

Abstract

The invention relates to a distributive control and double-clock asynchronous sending and receiving module and an FIFO (First In First Out) device. The distributive control and double-clock asynchronous sending and receiving module is that write data are transmitted by a source synchronization mode; a clock tree of a sending side is not distributed to a receiving side module, so that a real local cock domain can be achieved, and the cost of physically-achieved clock tree balance is decreased; a set of read pointers and write pointers is arranged in each of the sending side and the receiving side, and the two sets of read pointers and write pointers synchronously vary through read pulse and write pulse; FIFO full determining logic is allocated to the sending side, and empty determining logic is allocated to the receiving side, so that the distributive control is realized; the read pulse and the write pulse, instead of read pointers and the read pointers and synchronous full and empty signals, are transmitted between the receiving side and the sending side, and therefore, the quantity of control signals for transmission crossing the clock domain can be further decreased.

Description

technical field [0001] The invention relates to a dual-clock asynchronous FIFO device in the technical field of ultra-large-scale integrated circuits, in particular to a distributed control dual-clock asynchronous sending and receiving module and a FIFO device. Background technique [0002] The GALS (Globally Asynchronous Locally Synchronous) method is generally used in the design of ultra-large-scale digital circuits to realize the mixture of asynchronous and synchronous designs. The traditional synchronous design technology is used inside each module, and the signal transmission between these synchronous modules adopts asynchronous mode. This design method simplifies the design complexity of the VLSI chip, but introduces the synchronization problem of signal transmission between different clock domains. How to carry out reliable and efficient data asynchronous transmission between different modules has become one of the keys of GALS design. [0003] Dual-clock FIFO (dual...

AI Technical Summary

Problems solved by technology

However, with the expansion of chip scale and the increase of clock types, especially the overall increase in the frequency of different operating clocks in the chip, it brings great difficulties to the clock tree design and the delay control of signals between control modules.

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