Distributive control and double-clock asynchronous sending and receiving module and FIFO (First In First Out) device

A distributed control and asynchronous transmission technology, applied in the directions of generating/distributing signals, data conversion, instruments, etc., can solve problems such as difficulty in delay control of clock tree signals, and achieve the effect of reducing complexity and balance overhead.

CN104484011AInactive Publication Date: 2015-04-01上海高性能集成电路设计中心
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Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
Publication Date
2015-04-01
Estimated Expiration
Not applicable · inactive patent

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Abstract

The invention relates to a distributive control and double-clock asynchronous sending and receiving module and an FIFO (First In First Out) device. The distributive control and double-clock asynchronous sending and receiving module is that write data are transmitted by a source synchronization mode; a clock tree of a sending side is not distributed to a receiving side module, so that a real local cock domain can be achieved, and the cost of physically-achieved clock tree balance is decreased; a set of read pointers and write pointers is arranged in each of the sending side and the receiving side, and the two sets of read pointers and write pointers synchronously vary through read pulse and write pulse; FIFO full determining logic is allocated to the sending side, and empty determining logic is allocated to the receiving side, so that the distributive control is realized; the read pulse and the write pulse, instead of read pointers and the read pointers and synchronous full and empty signals, are transmitted between the receiving side and the sending side, and therefore, the quantity of control signals for transmission crossing the clock domain can be further decreased.
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Description

technical field

[0001] The invention relates to a dual-clock asynchronous FIFO device in the technical field of ultra-large-scale integrated circuits, in particular to a distributed control dual-clock asynchronous sending and receiving module and a FIFO device. Background technique

[0002] The GALS (Globally Asynchronous Locally Synchronous) method is generally used in the design of ultra-large-scale digital circuits to realize the mixture of asynchronous and synchronous designs. The traditional synchronous design technology is used inside each module, and the signal transmission between these synchronous modules adopts asynchronous mode. This design method simplifies the design complexity of the VLSI chip, but introduces the synchronization problem of signal transmission between different clock domains. How to carry out reliable and efficient data asynchronous transmission between different modules has become one of the keys of GALS design.

[0003] Dual-clock FIFO (dual...

Examples

Embodiment Construction

[0023] Below in conjunction with specific embodiment, further illustrate the present invention. It should be understood that these examples are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the teachings of the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims of the present application.

[0024] The first embodiment of the present invention relates to a distributed control dual-clock asynchronous sending module, such as figure 1 As shown, it includes a source synchronous signal generation logic circuit and a full flag generation logic circuit connected to each other, and the source synchronous signal generation logic circuit includes a write pulse generation circuit and a write data path, and the write pulse gen...