Method for realizing fan-out wafer encapsulation by preparing bumps on chip in advance

Abstract

The invention discloses a method for realizing fan-out wafer encapsulation by preparing bumps on a chip in advance. According to the method, the bumps are prepared on the chip in advance, an electroplating metal (such as Cu) method can be adopted to realize preparing of the bumps on the chip and a simpler efficient wafer chip bonding pad conducting wire bonding method is also can be adopted to realize preparing of the bumps on the chip (materials can be metal, such as Cu, Ag alloy); the extension of a chip circuit is rapidly and simply realized through the bumps of the chip; on the basis of the extension circuit which is realized through the bumps, a graphic modeling method of a substrate is combined so as to realize the redistribution of the output circuit of the chip, and finally a FOWLP encapsulation structure is obtained after reballing. The process of redistribution eliminates a photoprint technology in a semiconductor technology, so that the scheme provided by the invention has a certain advantages on the aspects of encapsulation efficiency and final cost.

Description

technical field [0001] The invention relates to a method for realizing fan-out wafer packaging (FOWLP) by pre-preparing bumps on a chip, and belongs to the technical field of integrated circuit chip packaging. Background technique [0002] 1) Infineon eWLP package. Such as figure 1 As shown, the chip 1 is attached to the carrier through the adhesive film in a face-down manner, and then plastic-encapsulated (see the plastic package 10 ). Subsequent RDL (Redistribution Line: rewiring) process (see rewiring layer 11) completes as follows figure 1 The FOWLP (Fan-Out Wafer Package) package structure shown. From the perspective of the process, its main disadvantage is that it needs to use semiconductor Photolithography (photocopying process), and the cost of corresponding equipment and process is relatively high. [0003] 2) Freescale RCP package structure. See the implementation process [0004] http: / / www.freescale.com / webapp / sps / site / overview.jsp?code=ASIC_LV3_PACKAGING_R...

AI Technical Summary

Problems solved by technology

From the perspective of the process, its main disadvantage is that it needs to use semiconductor Photolithography (photocopying process), and the cost of corresponding equipment and process is relatively high.

Its main disadvantage is that it needs to complete electroplating in the reserved holes of the substrate and lead out the circuit pads, and the cost of electroplating and the process are relatively difficult.

From the perspective of the process, even if the bumps on the chip are used, some processes still need to use the photocopying process, and the relative cost is relatively high

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