A FPGA-based filter with configurable coefficients, electronic equipment and filtering method

Abstract

The invention relates to a filter with configurable coefficients based on FPGA, which is connected to an external MCU and updates the filter coefficients through the external MCU. The filter includes: control logic, with coefficient reading address lines and data reading and writing address lines; A plurality of coefficient memories arranged in parallel are used to store filter coefficients, the filter coefficients in each coefficient memory are arranged in series with each other, the filter coefficients in the plurality of coefficient memories are connected end to end, the coefficient memories are coupled to the control logic and the external MCU, and A filter coefficient update channel is formed with an external MCU, and there are update coefficient address lines in the filter coefficient update channel; a plurality of sampling data memories; each of the plurality of coefficient memories and each of the plurality of sampling data memories are coupled to a plurality of multiplication Each of the multipliers is connected to the accumulator, and under the control of the control logic, the filter operation result is output through the flip-flop. The invention improves the processing speed of the filter.

Description

technical field [0001] The invention relates to FPGA, in particular to an FPGA-based filter with configurable coefficients, electronic equipment and a filtering method. Background technique [0002] FPGA (Field-Programmable Gate Array, that is, Field Programmable Gate Array), which is a product of further development on the basis of programmable devices such as PAL, GAL, and CPLD. It emerged as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of original programmable device gates. FPGA has a regular internal logic array and rich connection resources, which is especially suitable for digital signal processing tasks. Compared with general-purpose DSP chips dominated by serial operations, its parallelism and scalability are better. Using FPGA multiply-accumulate The fast algorithm can design a high-speed FIR digital filter. ...

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Problems solved by technology

but, figure 2 In the FIR filter, it takes several clock cycles to output. At the same time, the internal clock cycle is also affected by the operation speed of the multiplier, so the processing speed of the FIR filter with this structure is slow.

[0013] With the increasing complexity of signal processing in the actual system, a large amount of signal filtering processing work is often required in the system. In the traditional method, an FIR filter module is independently configured for each filter, which requires a lot of FPGA system resources. consumption is very large

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