FPGA-based configurable-coefficient filter and filtering method, and electronic equipment

Abstract

The invention relates to an FPGA-based configurable-coefficient filter. The FPGA-based configurable-coefficient filter is connected to an external MCU, and coefficients of the filter are updated through the external MCU. The filter comprises a control logic with a coefficient read address line and a data read and write address line, a plurality of coefficient memorizers arranged in parallel and used for storing the filtering coefficients, and a plurality of sample data memorizers, wherein filtering coefficients in each coefficient memorizer are mutually arranged in a serial manner, the filtering coefficients of the coefficient memorizers are connected end to end, the coefficient memorizers are coupled with the control logic and the external MCU, and form channels for updating of the coefficients of the filter with the external MCU, and updated coefficient address lines are arranged in the channels for updating of the coefficients of the filter; each coefficient memorizer and each sample data memorizer are coupled with the corresponding multiplier of a plurality of multipliers, and the multipliers are connected to an accumulator; under the control of the control logic, a filtering operation result is output by a trigger. According to the filter provided by the invention, the processing speed is increased.

Description

technical field [0001] The invention relates to FPGA, in particular to an FPGA-based filter with configurable coefficients, electronic equipment and a filtering method. Background technique [0002] FPGA (Field-Programmable Gate Array, that is, Field Programmable Gate Array), which is a product of further development on the basis of programmable devices such as PAL, GAL, and CPLD. It emerged as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of original programmable device gates. FPGA has a regular internal logic array and rich connection resources, which is especially suitable for digital signal processing tasks. Compared with general-purpose DSP chips dominated by serial operations, its parallelism and scalability are better. Using FPGA multiply-accumulate The fast algorithm can design a high-speed FIR digital filter. ...

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Problems solved by technology

but, figure 2 In the FIR filter, it takes several clock cycles to output. At the same time, the internal clock cycle is also affected by the operation speed of the multiplier, so the processing speed of the FIR filter with this structure is slow.

[0013] With the increasing complexity of signal processing in the actual system, a large amount of signal filtering processing work is often required in the system. In the traditional method, an FIR filter module is independently configured for each filter, which requires a lot of FPGA system resources. consumption is very large

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