A duty ratio adjustment circuit

Abstract

The invention discloses a duty cycle corrector, which comprises a single-stage CML_Latch, a two-stage CML_Latch and CML_AND, wherein a difference clock CLK is respectively connected to the input ends of clock signals of the single-stage CML_Latch and the two-stage CML_Latch, a differential signal Vin is connected to the input end of a differential signal of the two-stage CML_Latch, the output end of the differential signal of the two-stage CML_Latch is connected to the input end of a differential signal of the single-stage CML_Latch, a first input of the CML_AND is connected to the output end of the differential signal of the single-stage CML_Latch, and a second input of the CML_AND is connected to the output end of the differential signal of the two-stage CML_Latch. According to the duty cycle corrector, adjustment of a duty ratio can be implemented through the single-stage CML_Latch, the two-stage CML_Latch and the CML_AND, and the structure is simple; when the number of high level cycles is one more than the number of low level cycles, firstly, the output is subjected to lag input for a half of clock cycle through the single-stage CML_Latch, and then the input and the output of the single-stage CML_Latch pass through the CML_AND to change the half cycle of the high level is to the low level, so that the signal without 50% of duty ratio is adjusted to the signal with 50% of duty ratio, adjustment of 50% of duty ratio is implemented when a frequency dividing ratio is an odd number, and the application range is wide.

Description

technical field [0001] The invention relates to a channel frequency divider circuit of a clock distributor, in particular to a duty ratio adjustment circuit. Background technique [0002] With the improvement of the scientific and technological content of modern warfare, the amount of information transmission and processing has increased geometrically, and more and more high-speed processing digital circuits have put forward higher and higher requirements for the performance of the clock source. Among them, the clock distributor has been widely researched and applied for its advantages of low jitter, flexible configuration, high reliability, low power consumption, and easy integration. Modern high-speed digital circuits, high-speed AD / DA sampling, digital DDS, digital microprocessors and RF circuit technology demand for clock signals, so that clock distributor technology develops rapidly and is widely used, becoming a dazzling star in clock source technology . [0003] The...

AI Technical Summary

Problems solved by technology

[0004] The existing duty ratio adjustment circuit cannot adjust the duty ratio of the output signal to 50% when the frequency division ratio is an odd number

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