Duty ratio adjusting device and method of resonance system

Abstract

The invention discloses a duty ratio adjusting device and method of a resonance system. The device comprises a resonance system and a duty ratio adjusting device connected with the resonance system, the resonance system comprises a clock driver, a first capacitor connected with the clock driver and an inductor connected with the first capacitor, and the other end of the inductor is connected withan intermediate point of a decoupling capacitor to form a first intermediate node; the duty ratio adjusting device is used for detecting the duty ratio of the clock signal output by the clock driver and / or detecting the voltage value of the first intermediate node, and adjusting the duty ratio of the clock signal input to the clock driver according to the duty ratio output by the clock driver and / or the voltage value of the first intermediate node. The circuit is simple in structure, can precisely adjust the duty ratio of a resonance system, and guarantees the integrity of a clock signal waveform to the maximum degree.

Description

technical field [0001] The invention relates to a duty ratio detection and adjustment technology, in particular to a duty ratio adjustment device and method for a resonant system. Background technique [0002] With the development of integrated circuit technology, the scale of the chip is getting bigger and bigger, and the clock mesh is getting bigger and bigger, which will bring problems of power consumption and clock skew. The LC resonant clock generates and distributes clock signals through the LC resonant circuit, which can better solve the problem of large-scale integrated circuit chips (such as processors, GPU (Graphics Processing Unit, graphics processor), FPGA (Field-Programmable Gate Array, field programmable Gate array), TPU (Tensorprocessing unit, tensor processor)) power consumption, clock skew and jitter problems. Wherein, the resonant frequency of the LC resonant clock f=1 / (2*π*sqrt(LC)). Among them, C is the equivalent parasitic capacitance of the clock grid...

AI Technical Summary

Problems solved by technology

[0004] However, due to the existence of parasitic capacitance and resistance, the upper and lower driving capabilities of the clock driver are not equal, resulting in the duty cycle of the clock signal in the LC resonant clock (the ratio of the high or low level of the signal in one cycle; in this case, the correct duty cycle The ratio is 50%) deviation, and the duty cycle deviation causes the voltage of the virtual point to deviate from 1 / 2VDD, and the reaction of the voltage of the virtual point to deviate from 1 / 2VDD will cause the waveform distortion of the clock signal in the LC resonant clock

like Figure 1a In, the virtual point voltage deviation, resulting in Figure 1b Distorted clock signal waveform in

[0005] In order to solve the problem of distortion of the clock signal waveform caused by the above-mentioned duty cycle and the deviation of the virtual point voltage, it is necessary to provide a technology for correcting and adjusting the duty cycle of the resonant clock

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