STACKED 3D MEMORY and manufacturing method thereof

Abstract

A memory can include a plurality of memory blocks, including a first block and a second block disposed over the first block. An isolation layer is disposed in this structure, between the first and second blocks to isolate the vertical conductors in the memory kernels of the first and second blocks. Access conductors are provided outside the kernels, such as adjacent the memory blocks or through regions of the blocks that only include decoding element. The access conductors are coupled to the decoding elements in the first and second blocks, and provide for connection of the memory cells to peripheral circuits.

Description

technical field [0001] The present invention relates to high density memory technology, including technology of 3D arrays of memory cells. Background technique [0002] High-density flash memory is used as non-volatile storage in many systems. NAND flash memory is one of the common structures, and is usually arranged in a two-dimensional memory cell array. As manufacturing technology advances, the nodes (nodes) become smaller and smaller, and the two-dimensional NAND flash memory has reached its physical limit. Therefore, many other techniques have been developed. [0003] In the trend of achieving high storage capacity of flash memory and other types of memory, designers have devoted themselves to finding technologies for stacking multiple layers of memory cells to achieve higher storage capacity and lower cost per bit. For example, in the IEEE International Electronic Components Conference on December 11-13, 2006, Mr. Lai and others published "A Multi-Layer Stackable Th...

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Problems solved by technology

However, the structure with high aspect ratio is more difficult to etch, for example, the intermediate structure may break during the process, etc., so this structure also has its limitations

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