Memory array structure, method of operation and method of manufacture thereof

Abstract

The invention discloses a memory array structure, an operation method and a manufacturing method thereof. The memory array structure includes a ring circuit pattern, an array area and a contact area; the ring circuit pattern includes a plurality of word lines; the array area includes a first array, a second array and a plurality of bit lines; the first array includes a part The word line, a first ground selection line and a first series selection line, the first ground selection line and the first series selection line are located on both sides of the word line; the second array includes another part of the word line, a second ground selection line The selection line and a second serial selection line, the second ground selection line and the second serial selection line are located on both sides of the word line; the bit line is located in the first array and the second array and spans the first array and the second array; The contact area has a plurality of contact points, and the word line is electrically connected with an external circuit through the contact points.

Description

technical field [0001] The present invention relates to a memory array structure and its operating method, and in particular to a memory array structure with a circular circuit pattern and its operating method. Background technique [0002] With the advancement of memory manufacturing technology, the demand for storage devices also tends to be smaller in size and larger in storage capacity. To meet this demand, it is necessary to manufacture memory devices with high device density. However, in a memory device with high device density, the reduced circuit pattern width will increase the resistance, and the reduced space will cause the increased capacitance, thus causing RC delay (RC delay). The RC delay not only reduces the data transmission rate, but also reduces the reliability of the storage device. [0003] In addition, the double patterning process used in general memory devices requires three exposure, development / etching steps including cutting patterns, and the comp...

AI Technical Summary

Problems solved by technology

However, in a memory device with high device density, the reduced circuit pattern width will cause an increase in resistance, and the reduced space will cause an increase in capacitance, thus causing the phenomenon of RC delay (RC delay)

RC delay will not only reduce the rate of data transmission, but also reduce the reliability of the storage device (reliability)

[0003] In addition, the double patterning process used in general storage devices requires three exposure, development / etching steps including cutting patterns, and the complex process will also cause expensive manufacturing costs

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