Method and circuit for improving margin for setup time and hold time of input signal of time sequence device

Abstract

The invention relates to a circuit for improving margin for setup time and hold time of an input signal of a time sequence device. The circuit comprises a first input end, a second input end and an output end. The first input end inputs the input signal. The second input end inputs a first clock signal. The output end is connected with the time sequence device. The first clock signal is also a clock signal of the time sequence device. The circuit comprises a first delay cell and a first latch. The first delay cell inputs the first clock signal and delays a first preset time, and then outputs a second clock signal. The data end of the first latch is connected with the input signal. The clock end of the first latch is connected with the second clock signal. The output end of the first latch outputs a first widening signal. The first widening signal is used for widening the width of an effective level in the input signal backwards.

Description

technical field [0001] The invention relates to a digital circuit, in particular to a method and a circuit for improving the setup time and the hold time margin of an input signal of a sequential device. Background technique [0002] With the development of electronic technology, the operating frequency of digital electronic systems is getting higher and higher, and the requirements for the timing relationship of signals are becoming more and more stringent. In order to ensure that the digital electronic system can work stably, it is necessary to test the timing parameters of the sequential devices in the system. These timing parameters include signal setup time (setup time) and hold time (hold time). [0003] The setup time and hold time are the time requirements for testing sequential devices between input signals (such as digital signals, address signals, chip select signals, etc.) and clock signals, which characterize the input duration of data before and after clock ed...

AI Technical Summary

Problems solved by technology

[0006] However, in actual digital electronic systems, there may still be individual sequential devices or circuits that require a long setup time and / or hold time. As a result, the sum of setup time and hold time is very close to one clock cycle

In this case, through the aforementioned relative relationship adjustment between the input signal and the clock signal, although it is possible to meet the requirements of the setup time and the hold time at the same time, such a tight timing design means that there is no margin to deal with the deviation of the actual chip ( On Chip Variation, OCV), such as clock signal jitter (jitter) and skew (skew), which may lead to poor system stability

[0007] Faced with the aforementioned problems, some digital electronic systems have to reduce the clock frequency and increase the clock period to meet the requirements of setup time and hold time, at the cost of sacrificing the performance of the system

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