Field programmable logic array and serial data receiving and converting method

Abstract

The invention discloses a field programmable logic array. Through a control unit, the output of N analog-digital converter chips and a phase lock loop are independently controlled, the position regulation of N output clock phases output by the phase lock loop and the word regulation of parallel data output by N deserialized units are independently realized, and the dynamic compensation of time migration between a latch clock and a data channel is realized; then, the N analog-digital converter chips are controlled to output normal signals; and N deserialized units generate and output parallel data under a normal work state according to the normal signals output by the N analog-digital converter chips and the regulated output clock phase output by the phase lock loop. The field programmable logic array only needs one phase lock loop to realize regulation and parallel output, so that the time migration from the latch clock to the data channel can be dynamically compensated while the resources of the phase lock loop of the field programmable logic array are fully utilized.

Description

technical field

[0001] The invention relates to the technical field of data acquisition, in particular to a field programmable logic array and a method for receiving and converting serial data. Background technique

[0002] In the medical ultrasound imaging system, the analog-to-digital converter ADC chip uses a small number of pins to serially output the collected echo signals, thereby realizing high-speed sampling of the commonly used 128 echo signals. FPGA (Field-Programmable Gate Array, Field Programmable Logic Array) uses the system clock source to perform serial / parallel conversion (serial-to-parallel conversion) on the serial data output by the ADC chip.

[0003] At present, high-end FPGA uses its internal PDA (dynamic phase alignment, dynamic phase adjustment) circuit to realize the aforementioned serial-to-parallel conversion, while low-end FPGA realizes serial-to-parallel conversion through the following methods: figure 1 As shown, several ADC chips 101 share a PL...

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