A Method for Finding Fragile Branches of FPGA Programs Based on Ant Colony Algorithm
A technology of ant colony algorithm and program, applied in calculation, calculation model, detection of faulty computer hardware, etc., can solve problems such as difficult evaluation of FPGA program reliability
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Embodiment 1
[0073] In VHDL, in the hierarchical relationship of modules, the bottom entity (module) is the most basic functional module, and the so-called topological connection refers to the port connection relationship between these basic functional modules. The port connections of modules (components) are defined in the upper modules that call these components. Only by finding out the module calling relationship in the complete VHDL program can the port connection relationship between the basic function modules be determined.
[0074] VHDL is a hardware description language with a strict grammatical structure. According to the grammatical structure, we can use fixed keywords to find statements describing the topological connection relationship: entity definition statement, port declaration statement, component instantiation statement and port mapping statement. The entity definition statement contains the name information of the entity. Since the VHDL language is written in units of en...
Embodiment 2
[0132] On the basis of Embodiment 1, further, the engineering code is tested, and its implementation process includes the following steps:
[0133] (1) read in the FPGA program; input the FPGA program into the execution program;
[0134] (2) determine the module number; In the present embodiment, through program detection, the module number that the FPGA program of input comprises is 8;
[0135] (3) Locate to the beginning of the module; through the search mode, find the enlightenment module of 8 modules;
[0136] (4) Use the port keyword to determine the port of each module, and record the port name and port quantity. The test structure is shown in the following table:
[0137]
[0138] (5) Use the component keyword to determine the component, and record the name of the component, the port name and quantity of the component;
[0139] (6) Use the port map keyword to determine the connection relationship of the components;
[0140] (7) Repeat (4)~(6) until every module is...
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