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The Method of Measuring the Parasitic Capacitance on the Line Using ate

A technology of parasitic capacitance and measurement circuit, which is applied in the field of integrated circuit testing, can solve the problem that parasitic capacitance cannot be measured quickly and accurately, and achieve the effect of convenient measurement, fast and accurate measurement

Active Publication Date: 2018-04-27
SINO IC TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The purpose of the present invention is to provide a method of using ATE to measure the parasitic capacitance on the line to solve the problem that the parasitic capacitance in the test path cannot be quickly and accurately measured during the ATE test

Method used

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  • The Method of Measuring the Parasitic Capacitance on the Line Using ate
  • The Method of Measuring the Parasitic Capacitance on the Line Using ate

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Embodiment Construction

[0026] The specific implementation manner of the present invention will be described in more detail below with reference to schematic diagrams. The advantages and features of the present invention will become apparent from the following description and claims. It should be noted that, the accompanying drawings are all in a very simplified form and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

[0027] The invention provides a method for measuring the parasitic capacitance on the line by using ATE, such as figure 1 shown, including the following steps:

[0028] S1: Select the test path to be measured.

[0029] S2: ATE defines a vector generation data and a vector, and applies a first voltage U to the test path according to the vector generation data and the vector 1 The test path is charged.

[0030] There are several hundred or more than two thousand test channels on the ATE test...

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Abstract

The invention provides a method for measuring the parasitic capacitance of a circuit through ATE, and the method comprises the steps: employing a measurement assembly of the ATE to measure a stable charging voltage and discharge voltage of a test circuit, i.e., a first voltage and a second voltage; measuring the duration (vector period * number of vector rows) when the voltage of the test circuit is changed to the second voltage from the first voltage, thereby quickly and accurately measuring the parasitic capacitance of the test circuit through the charging and discharging time. When a testing channel and a load plate of the ATE are changed, the measurement of the parasitic capacitance of different test circuits can be quickly and conveniently completed only through the modification of vector generation data.

Description

technical field [0001] The invention relates to the field of integrated circuit testing, in particular to a method for measuring parasitic capacitance on a line by using ATE. Background technique [0002] Integrated circuit devices need to undergo ATE mass production testing before sales. In general, the test specification of the device under test requires that the output port of the device under test is under a certain load capacitance. Standard interface for automatic test equipment). Generally, the load board is a printed circuit board, on which the peripheral circuits required for testing can be placed, and the pins of the device under test are connected to resources such as power supply and digital channels of the ATE test. pin. [0003] However, since the traces and peripheral circuits connected to each channel on the load board will generate a certain parasitic capacitance, the parasitic capacitance will affect the test results of the device under test, especially ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R27/26
Inventor 王华祁建华刘远华汤雪飞季海英王锦
Owner SINO IC TECH