A low-temperature polysilicon transistor array substrate, its preparation method, and display device
A transistor array, low-temperature polysilicon technology, applied in transistors, semiconductor/solid-state device manufacturing, semiconductor devices, etc., can solve the problems of leakage current, easy generation of hot carriers, large concentration gradient of doping ions, etc., to prevent leakage current , Improve the effect of interface defects
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Embodiment 1
[0041] like Figure 3-4 As shown, this embodiment provides a low-temperature polysilicon transistor array substrate, including:
[0042] A substrate 1, a polysilicon semiconductor active region disposed on the substrate 1, and a gate 4 insulated from the polysilicon semiconductor active region 2, and dielectric spacers 7 are provided on both sides of the gate 4, The dielectric spacer 7 surrounds the side of the gate 4 and covers the end of the polysilicon semiconductor active region 2; the position of the polysilicon semiconductor active region 2 corresponding to the dielectric spacer 7 includes a buffer District 8.
[0043] In the low-temperature polysilicon transistor array substrate of this embodiment, since dielectric spacers 7 are provided on both sides of the gate 4, a buffer zone 8 can be formed corresponding to the polysilicon semiconductor active region 2 in the subsequent ion implantation doping process. The concentration of impurity ions in 8 is lower than the con...
Embodiment 2
[0051] like Figure 5-10 As shown, this embodiment provides a method for preparing the above-mentioned low-temperature polysilicon transistor array substrate, including:
[0052] Step 1: forming a polysilicon semiconductor active layer on the substrate;
[0053] like Figure 5 As shown, a layer of amorphous silicon layer is deposited on the substrate 1, and then, after dehydrogenation treatment, laser annealing process, metal-induced crystallization process, solid phase crystallization process, etc. are used to crystallize the amorphous layer to form a polysilicon semiconductor active layer; the pattern of the polysilicon semiconductor active region 2 is formed by a patterning process.
[0054] Step 2: forming a gate insulating layer on the polysilicon semiconductor active layer;
[0055] like Image 6 As shown, the gate insulating layer 3 is deposited by the PEVCD method, and the specific method is within the scope of the prior art and will not be repeated here.
[0056]...
Embodiment 3
[0070] This embodiment provides a display device that adopts the above-mentioned low-temperature polysilicon transistor array substrate
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