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sic MOSFET structure and manufacturing method thereof

A manufacturing method and a three-layer structure technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of contrast layer mobility, high power consumption and efficiency loss, and improve the short channel effect , enhance the channel stress, increase the effect of carrier mobility

Active Publication Date: 2015-12-02
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, currently fabricated SiC MOSFETs exhibit very poor inversion layer mobility (about 1 cm2 / Vs), which is a hundred times lower than the expected inversion layer mobility, resulting in large power consumption and efficiency loss, making SiC MOSFETs with Their Si counterparts perform essentially the same
The lower mobility of the inversion layer is mainly due to the current conduction at the poor interface (interface) between the gate oxide and SiC, specifically, the SiO2 between the gate oxide and SiC. 2 / SiC interface has a large number of interfacial traps that trap electrons that facilitate current flow, resulting in very poor inversion layer mobility

Method used

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  • sic MOSFET structure and manufacturing method thereof
  • sic MOSFET structure and manufacturing method thereof
  • sic MOSFET structure and manufacturing method thereof

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Embodiment 1

[0042] Such as figure 2 As shown, the present embodiment provides a SiC MOSFET manufacturing method, comprising the following steps:

[0043] S201, providing a substrate formed with a SiC channel region;

[0044] S202, forming a SiC layer and a SiGe layer stacked from bottom to top in the defined area of ​​the SiC channel region;

[0045] S203, sequentially forming a gate stack structure including a gate oxide layer and a gate layer, and sidewalls surrounding the gate stack structure over the substrate;

[0046] S204, forming a SiGe source region and a SiGe drain region in the substrate, and a channel between the SiGe source region and the SiGe drain region is a SiC layer and a SiGe layer stacked along a direction from the substrate to the gate.

[0047] Please refer to Figure 3A As shown, in step S201, the provided substrate 300 may be a pure Si (silicon) substrate, a SiC substrate, a Si-on-insulator (SOI) substrate, a SiC-on-insulator substrate, or a Si substrate with a...

Embodiment 2

[0055] Such as Figure 4 As shown, the present embodiment provides a SiC MOSFET manufacturing method, comprising the following steps:

[0056] S401, providing a substrate formed with a SiC channel region;

[0057] S402, etching and removing a certain thickness of the SiC channel region, and sequentially depositing a SiGe layer and a stressed Si layer in the limited area where the thickness is removed;

[0058] S403, sequentially forming a gate stack structure including a gate oxide layer and a gate layer, and sidewalls surrounding the gate stack structure on the substrate including the stressed Si layer;

[0059] S404, forming a SiGe source region and a SiGe drain region in the substrate, and a channel between the SiGe source region and the SiGe drain region is a SiC layer and a SiGe layer stacked along a direction from the substrate to the gate.

[0060] Please refer to Figure 5A As shown, in step S401 , the provided substrate 500 may be a pure Si (silicon) substrate, a S...

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Abstract

The invention provides a SiC MOSFET structure and a manufacturing method thereof. A SiC-SiGe stacking channel structure is formed on the basis of an original SiC channel region, meanwhile a SiGe source region and a SiGe drain region are formed, crystal lattice dislocation between SiC and SiGe is utilized to increase channel region stress, and carrier mobility of a channel region is improved; a SiC-SiGe-Si stacking channel structure is formed on the basis of the original SiC channel region, channel stress is strengthened, nitrogen, fluorine and other ions are injected into the SiC channel region to overcome the defect of an interface of the SiC channel region, Ge diffusion of the source region and the drain region is restrained, short-channel effects are improved, and the carrier mobility is increased.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a SiC MOSFET structure and a manufacturing method thereof. Background technique [0002] With the continuous reduction of device feature size, the short channel effect (SCE), drain barrier lowering (DIBL) effect and hot carrier effect of the device are becoming more and more serious, which degrades the performance of the device. The short channel effect of the device is mainly due to the charge sharing with the decrease of the channel length, that is, the charge in the depletion region under the gate is no longer completely controlled by the gate, and part of it is controlled by the source and drain, and with the channel length The reduction of the depletion region controlled by the gate reduces the charge, and more gate voltage is used to form the inversion layer, so that the gate voltage reaching the threshold is continuously reduced. As a result, the threshold volta...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/10H01L29/24H01L29/78H01L21/265H01L21/336
Inventor 赵猛
Owner SEMICON MFG INT (SHANGHAI) CORP
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