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A Phase Locked Loop with Low Phase Noise

A phase-locked loop and phase detector technology, applied in the direction of automatic power control, electrical components, etc., can solve the problem of large phase noise of the phase-locked loop, achieve small dead zone of high-frequency phase detection, reduce phase noise, and get rid of the detection of phase noise. Effect of Phase Velocity Limitation

Active Publication Date: 2018-03-27
SUN YAT SEN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The purpose of the present invention is to provide a phase-locked loop with low phase noise, which aims to solve the technical defect of excessive phase noise of the existing phase-locked loop

Method used

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  • A Phase Locked Loop with Low Phase Noise
  • A Phase Locked Loop with Low Phase Noise
  • A Phase Locked Loop with Low Phase Noise

Examples

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Embodiment Construction

[0025] The embodiments of the present invention will be further described below in conjunction with the drawings.

[0026] See figure 2 , figure 2 It is a phase-locked loop with low noise phase provided by the embodiment of the present invention. in figure 2 In the illustrated embodiment, the low phase noise phase-locked loop of this structure includes a frequency-to-digital converter 110, an oscillator frequency calibrator 120, a loop bandwidth calibrator 130, a digital oscillator 190, a phase detector 140, and a time digital converter. The converter 150, the filter 160, and the clock distribution module 180.

[0027] in figure 1 In the illustrated embodiment, the input terminal of the frequency-to-digital converter 110 receives the input signal, and the output terminal is connected to the input terminals of the oscillator frequency calibrator 120 and the loop bandwidth calibrator 130 respectively. The output terminal of the oscillator frequency calibrator 120 is connected to ...

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Abstract

The invention discloses a phase-locked loop with low phase noise. The phase-locked loop includes a frequency-to-digital converter, an oscillator frequency calibrator, a loop bandwidth calibrator, a digital oscillator, a phase detector, a time-to-digital converter, a filter, and a clock distribution module, wherein the frequency-to-digital converter The input terminal of the oscillator receives the input signal, and the output terminal is respectively connected with the input terminal of the oscillator frequency calibrator and the loop bandwidth calibrator; the output terminal of the oscillator frequency calibrator is connected with the input terminal of the digital oscillator, The output terminal of the loop bandwidth calibrator is connected with the control terminal of the filter. The phase-locked loop with low phase noise involved in the embodiment of the present invention uses a high-resolution time-to-digital converter to realize the conversion of the phase difference, replaces the traditional digital phase detector, and gets rid of the limitation of the system clock frequency on the phase detection speed. The high-frequency phase detection dead zone becomes smaller, thereby greatly reducing the phase noise of the phase-locked loop.

Description

Technical field [0001] The invention relates to a phase-locked loop structure in the field of electronic technology, in particular to a phase-locked loop with low phase noise. Background technique [0002] A phase-locked loop is a feedback system in which a voltage-controlled oscillator (VCO) and a phase comparator are connected to each other so that the oscillator output can maintain a constant phase angle with respect to a reference signal. Phase-locked loops have applications in many fields, such as wireless communications, digital television, broadcasting and other fields. As attached figure 1 As shown, a phase-locked loop circuit is usually composed of the following modules: phase detector (PD), low-pass filter (LPF), voltage-controlled oscillator (VCO) and feedback loop (usually by a divider (DIV)) achieve). The phase detector compares the frequency and phase of the input reference signal and the signal of the feedback loop, and outputs a signal representing the differenc...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/08H03L7/099
Inventor 王自鑫陈弟虎何振辉何裕宁王敏刘伍兵
Owner SUN YAT SEN UNIV