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Method and device for reset control of power domain

A technology of reset control and power domain, applied in the direction of data reset device, etc., can solve problems such as the inability to meet the energy consumption requirements of large SOC chips, and achieve the effect of enhancing adaptability and robustness

Active Publication Date: 2018-01-26
FUZHOU ROCKCHIP SEMICON
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AI Technical Summary

Problems solved by technology

[0002] As the power consumption requirements of SOC chips are getting higher and higher, the traditional chip unified power supply method in the past can no longer meet the energy consumption requirements of large SOC chips. Therefore, the circuits in the chip are divided into multiple power domain circuits according to their functions or working methods. Each power domain is controlled by the power switch inside the chip, which can independently turn off a certain power domain in the chip. But this also brings some new problems, such as the need to design a Complex circuit operation timing to ensure correctness when the power domain is turned on

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  • Method and device for reset control of power domain
  • Method and device for reset control of power domain

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Embodiment Construction

[0031] Such as figure 1 As shown, in the reset control device of the power domain of the present invention, a clock circuit A1 and a common function circuit A2 are provided in the power domain A, and the device includes a wake-up source 1, a timing control unit 2, a power control unit 3, and a reset length information storage unit 4. Reset generation and holding unit 5, reset delay unit 6, reset delay length information storage unit 7, crystal oscillator clock circuit unit 8, and power ring 9 set one by one corresponding to the power domain; the wake-up source 1, timing control unit 2, The power control unit 3 and the power ring 9 are sequentially connected; the timing control unit 2, the reset generating and maintaining unit 5, and the reset delay unit 6 are sequentially connected to the common function circuit A2 in the power domain A, and the reset generating and maintaining unit 5 is also connected to To the clock circuit A1 in the power domain A; the crystal oscillator cl...

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Abstract

The present invention provides a reset control method and control device of a power domain. The method includes: the wake-up source receives a wake-up action command to initiate a wake-up action to the timing control unit; the timing control unit controls the reset generation and maintenance unit to generate a reset valid signal, and controls The power control unit opens the power ring of the corresponding power domain, so that the corresponding power domain enters the reset state immediately after being powered on; the reset generating and holding unit cancels the reset valid state according to the reset holding time length information; the clock circuit starts to work and generates a clock; The delay unit delays the received reset signal according to the reset delay length information and then sends it to the normal function circuit in the power domain, and the normal function circuit starts to work after receiving the delayed reset cancellation. The invention separately controls the reset of the clock circuit and the common function circuit, and further enhances the adaptability and robustness when the power domain is turned on.

Description

technical field [0001] The invention relates to a reset control method and device of a power domain. Background technique [0002] As the power consumption requirements of SOC chips are getting higher and higher, the traditional chip unified power supply method in the past can no longer meet the energy consumption requirements of large SOC chips. Therefore, the circuits in the chip are divided into multiple power domain circuits according to their functions or working methods. Each power domain is controlled by the power switch inside the chip, which can independently turn off a certain power domain in the chip. But this also brings some new problems, such as the need to design a Complicated timing of circuit operations to ensure correctness when power domains are turned on. In this sequence, how to minimize the risk of problems while maintaining strong adaptability and robustness. Especially in many advanced CPU or GPU designs, a large number of pipeline designs are used, ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F1/24
Inventor 廖裕民陈丽君叶院红
Owner FUZHOU ROCKCHIP SEMICON
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