Method and device for reset control of power domain
A technology of reset control and power domain, applied in the direction of data reset device, etc., can solve problems such as the inability to meet the energy consumption requirements of large SOC chips, and achieve the effect of enhancing adaptability and robustness
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[0031] Such as figure 1 As shown, in the reset control device of the power domain of the present invention, a clock circuit A1 and a common function circuit A2 are provided in the power domain A, and the device includes a wake-up source 1, a timing control unit 2, a power control unit 3, and a reset length information storage unit 4. Reset generation and holding unit 5, reset delay unit 6, reset delay length information storage unit 7, crystal oscillator clock circuit unit 8, and power ring 9 set one by one corresponding to the power domain; the wake-up source 1, timing control unit 2, The power control unit 3 and the power ring 9 are sequentially connected; the timing control unit 2, the reset generating and maintaining unit 5, and the reset delay unit 6 are sequentially connected to the common function circuit A2 in the power domain A, and the reset generating and maintaining unit 5 is also connected to To the clock circuit A1 in the power domain A; the crystal oscillator cl...
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