Clock control method and apparatus

Abstract

The present invention provides a clock control method and apparatus. The apparatus comprises a hibernation mode management module and a hibernation policy execution module. The hibernation policy execution module is such configured that: after a shallow hibernation mode is started and when a service module is running, a clock control device disables a non-working analog IP in the shallow hibernation mode according to a clock control policy acquired from a shallow hibernation register; and upon completion of running of the service module, the clock control device enables the analog IP disabled in the shallow hibernation mode according to the clock control policy acquired from the shallow hibernation register. The hibernation policy execution module is further such configured that: when a deep hibernation mode is started, the clock control device automatically disables a non-working analog I{ in the deep hibernation mode; and after the deep hibernation mode is started and in the advent of an external interruption, the clock control device automatically enables the analog IP disclosed in the deep hibernation mode. According to the present invention, the gate clock is automatically managed by using a hardware system, thereby greatly improving the processing performance.

Description

technical field [0001] The invention belongs to the field of clock control, in particular to a clock control method and device. Background technique [0002] Power consumption management has always been the key to chip development and design, and is the basis for the low-power consumption of the entire chip. A good power consumption management method can not only improve the operating speed of the entire chip, but also enable it to operate with low energy consumption and prolong the standby time. [0003] The traditional power management method is mainly realized by dividing its constituent modules into multiple clock regions, and then using the embedded software of DPM technology to manage the clock supply of each clock region, and completely shutting down the clocks of modules that do not participate in the current work input, to turn the clock supply back on when required to engage the work, [0004] As shown in Figure 1, the software configures the 1.1 register, and the...

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Problems solved by technology

[0006] The above methods require software personnel to be very clear about the operation process, which increases the complexity of the software and affects the performance of the chip.

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