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Memory control apparatus, information processing apparatus and control method thereof

A technology for information processing equipment and control equipment, which is applied in memory systems, electrical digital data processing, input/output processes of data processing, etc., and can solve problems such as performance degradation and time-consuming

Inactive Publication Date: 2015-09-30
CANON KK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

A full wipe of all data is time consuming and may cause performance degradation

Method used

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  • Memory control apparatus, information processing apparatus and control method thereof
  • Memory control apparatus, information processing apparatus and control method thereof
  • Memory control apparatus, information processing apparatus and control method thereof

Examples

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no. 1 example

[0071] Hereinafter, an example according to the present first embodiment in which a full erase area 1300 and a normal area 1310 have been set in the main area 410 of the link table 220 will be described.

[0072] Figure 12 is a flowchart showing processing of the flash memory controller 20 according to the first embodiment to set a full erase area in the main area of ​​the link table 220 . A program for executing the processing is stored in the ROM 111 , and the processing is realized by the CPU 110 executing the program.

[0073] This processing starts when the information processing apparatus according to the first embodiment is powered on. First, in step S1201, the CPU 110 judges whether there is a setting change for the full erase function; if there is such a setting change, the process proceeds to step S1202, and if there is no such setting change yet, the process Straight to the end. Note that the settings for the full erase function are held in the flash memory 30, ...

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Abstract

A memory control apparatus associates logical addresses with corresponding physical addresses in a non-volatile storage device, and divides the physical addresses in the non-volatile storage device into addresses for complete erasure and other addresses and manages those addresses in the divided manner if a complete erasure mode is set. In the case where data stored in the non-volatile storage device has been instructed to be erased based on a logical address, the memory control apparatus completely erases data at the physical address associated with the logical address in the case where the physical address belongs to the addresses for complete erasure, and cancels a link to the data at the physical address associated with the logical address in the case where the physical address does not belong to the addresses for complete erasure.

Description

technical field [0001] The present invention relates to a memory control device, an information processing device and a control method thereof. Background technique [0002] NAND flash memory controllers that control NAND flash memory are generally known to perform wear leveling to extend the lifetime of the NAND flash memory. Various methods are used for the wear leveling depending on the NAND flash memory controller, and the timing at which the wear leveling is performed also differs depending on the NAND flash memory controller. [0003] In the case of a structure in which the system controller is connected to the NAND flash memory controller, the following situation may occur: After wear leveling is performed, the data in the table managed by the system controller may be copied to other parts of the NAND flash memory. piece. Thus, even if the system controller erases given data for security purposes, it is possible that the data will remain in other locations. Thus, a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F3/06G06F12/02
CPCG06F3/0608G06F12/0246G06F2212/657G06F3/0652G06F12/10G06F2212/2022G06F2212/7205G06F3/0679G06F12/0253G06F3/0659G06F2212/1044G06F2212/7201G06F2212/152G06F3/061
Inventor 伊藤武弘
Owner CANON KK
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