On-board nand FLASH bad area management system

Abstract

The present invention provides a management system for satellite-borne NAND FLASH solid storage bad areas, including: four groups of FLASH storage chips, used for recording and replaying satellite load detection data, and providing chip status feedback information during solid storage erasing and writing processes And verification information; storage control FPGA, used to control the erasing, writing and reading operations of the FLASH memory chip, judge the quality of the block according to the chip feedback information and verification information of the FLASH memory chip, and facilitate the EEPROM to update the bad area table; EEPROM is used to store the bad area table information of the FLASH memory chip; the watchdog is used to prevent the storage control FPGA control signal terminal from being in an uncertain state and mistakenly write error information into the EEPROM during the power-on and power-off process of the single machine. The invention can be applied to the meteorological satellite data transmission sub-system, and the bad area management method effectively guarantees the correctness and integrity of the satellite on-orbit remote sensing data.

Description

technical field [0001] The invention relates to the field of satellite detection data access, in particular to the design of a satellite-borne NAND FLASH solid storage bad area management system. Background technique [0002] With the significant increase in the input rate of satellite loads, the demand for solid storage capacity has increased significantly, and the memory chips have been replaced by NAND FLASH series chips from SDRAM type. The memory capacity of the chip is 32Gbits. The newly adopted memory chip has the characteristics of high integration, the indicators meet the application requirements, the technology is relatively mature, and it has the experience of in-orbit flight verification. [0003] When used on a satellite, the storage module is composed of an ACTEL FPGA A54SX32A plus a NAND FLASH chipset, and uses (72, 64) Hamming check to enhance the anti-single event flipping capability of the FLASH storage board. One of the memory chips is used for EDAC verif...

AI Technical Summary

Problems solved by technology

However, due to the process structure of the NAND FLASH chip, some bad areas will appear during use, and the stand-alone machine must have the function of updating the bad area table in real time

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