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Dynamic and static mixed adder

An adder, dynamic and static technology, applied in the field of combined dynamic and static adders, can solve problems such as not being the highest efficiency, and achieve the effects of saving energy dissipation, avoiding signal contention, and simple circuit form

Active Publication Date: 2015-11-11
HEFEI UNIV OF TECH
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Problems solved by technology

[0002] With the advancement of VLSI technology, various digital electronic products are booming. In various applications, as the size of electronic products continues to shrink, battery capacity has gradually become a design bottleneck. It is feasible to reduce the operating voltage to reduce circuit power consumption, but But it is not the most efficient method. More data calculations can be performed under the same energy. This is the direction to improve circuit efficiency.

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  • Dynamic and static mixed adder
  • Dynamic and static mixed adder

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Embodiment Construction

[0023] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0024] Such as figure 1 As shown, the embodiment of the present invention provides a dynamic and static adder, which includes a static part 1 and a dynamic part 3, the static part 1 completes the carry operation of addition, and the output terminal of the static part 1 outputs a reverse carry signal, the output end of the static part 1 is connected to the input end of a first inverter 2, and the first inverter 2 outputs a carry signal;

[0025] The output terminal...

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Abstract

A dynamic and static mixed adder comprises a static part and a dynamic part, wherein the output end of the static part is connected with the input end of a first phase inverter; the first phase inverter is used for outputting a carry signal; the output end of the static part is further connected with the dynamic part; the dynamic part is used for finishing summation operation of addition; the output end of the dynamic part is connected with a second phase inverter; the dynamic part comprises a summing circuit and a potential holding circuit; the summing circuit is used for finishing summation operation of addition; and the potential holding circuit is connected with the output end of the second phase inverter and used for compensating charge of a floating node and reducing signal scramble during operation of the adder. The adder is simple in circuit form, slightly influenced by change of process parameters and capable of effectively working in a low-voltage environment; and through the potential holding circuit, originally the signal scramble in the operational process is avoided, the power consumption is reduced, and the energy utilization efficiency is highest near a critical voltage value.

Description

technical field [0001] The invention designs an adder module in the field of VLSI design, and in particular relates to a dynamic and static combined adder. Background technique [0002] With the advancement of VLSI technology, various digital electronic products are booming. In various applications, as the size of electronic products continues to shrink, battery capacity has gradually become a design bottleneck. It is feasible to reduce the operating voltage to reduce circuit power consumption, but However, it is not the most efficient method. More data calculations can be performed under the same energy. This is the direction to improve circuit efficiency. As the adder is an indispensable module in the middle of VLSI, reducing the pdp (powerdelayproduct) of the adder can effectively improve the energy efficiency of the circuit. Contents of the invention [0003] In order to solve the above-mentioned technical problems, the present invention provides a dynamic and static ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/50
Inventor 张章谢溪铮谢玉芳魏一勤解光军
Owner HEFEI UNIV OF TECH