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Wear balancing method of non-volatile memory based on multi-level cell

A technology of wear leveling and multi-layer units, applied in the direction of memory address/allocation/relocation, etc., can solve the problems of reduced service life and performance degradation, and achieve high service life, low space overhead, high service life and security Effect

Active Publication Date: 2015-11-18
HUAZHONG UNIV OF SCI & TECH
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Problems solved by technology

Increasing the exchange frequency will lead to performance degradation, and increasing the number of regions will worsen the unbalanced write traffic between regions, which will reduce the service life

Method used

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  • Wear balancing method of non-volatile memory based on multi-level cell
  • Wear balancing method of non-volatile memory based on multi-level cell
  • Wear balancing method of non-volatile memory based on multi-level cell

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Embodiment Construction

[0020] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not constitute a conflict with each other.

[0021] In order to facilitate understanding of the present invention, at first the following nouns appearing in the present invention are explained:

[0022]Physical row: The most basic access unit of the memory system. In different systems, the row size can be different, usually a row size can be 64 bytes, 128 bytes, 256 bytes.

[0023] Sub-storage area: composed of several physical rows, usu...

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Abstract

The invention discloses a wear balancing method of a non-volatile memory system based on a multi-level cell. The wear balancing method comprises the following steps: dividing each wafer in a storage region of the non-volatile memory system into a plurality of sub-storage regions; randomly exchanging data in a physical line in the sub-storage regions by using an algebra-based wear balancing algorithm after P writing requests are performed in each sub-storage region every time; and performing data exchange by selecting a hot sub-storage region and a cold sub-storage region in various sub-storage regions after T writing requests are performed in the storage region of the non-volatile memory system every time, wherein T is a region exchange interval, which is a predetermined value or a random number; the hot sub-storage region is the sub-storage region having more cumulative writing numbers; and the cold sub-storage region is the sub-storage region having less cumulative writing numbers. In combination with a table-based wear balancing algorithm and the algebra-based wear balancing algorithm, the wear balancing method disclosed by the invention has the advantages of being long in service life, safe and reliable.

Description

technical field [0001] The invention belongs to the field of solid-state storage, and more specifically relates to a wear leveling method of a multi-level unit-based nonvolatile memory system. Background technique [0002] With the development of multi-core technology, computer systems have higher and higher requirements for memory, including capacity, power consumption, performance, scalability and other aspects. The development of traditional dynamic random access memory (Dynamic Random Access Memory, DRAM) is limited in the face of new application environments due to the constraints of scalability and leakage power consumption. [0003] The emergence of new non-volatile memory (Non-VolatileMemory, NVM) technology provides a new solution for the development of memory systems. The current new non-volatile memory mainly includes phase change memory (PhaseChangeMemory, PCM) and memristor (ResistiveRandomAccessMemory, RRAM), which have the advantages of large capacity, low po...

Claims

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Application Information

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IPC IPC(8): G06F12/02
Inventor 冯丹周文刘景宁李峥鄢磊黄方亭
Owner HUAZHONG UNIV OF SCI & TECH
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