Optimization method for netlist logic redundancies in ASIC design and optimization system for netlist logic redundancy in ASIC design

Abstract

The invention relates to the technical field of chip design, in particular to an optimization method for netlist logic redundancies in ASIC (Application Specific Integrated Circuits) design and an optimization system for the netlist logic redundancies in the ASIC design. The method comprises the following steps of: performing targeted logic redundancy analytical processing on a netlist in the ASIC design process to obtain initial analysis data; extracting redundancy features in the initial analysis data, and recognizing the logic redundancies of the netlist; classifying the logic redundancies of the netlist by utilizing the redundancy features, and performing redundancy node division on the logic redundancies in a division mode corresponding to the affiliated class of the logic redundancies to obtain redundancy nodes of the logic redundancies; and deleting the logic redundancies by utilizing the redundancy nodes of the logic redundancies to obtain the optimized netlist. Compared with the prior art, the optimization method has the advantages that more classes of logic redundancies can be recognized and can be optimized; and different classes of logic redundancies can be automatically deleted, so that the logic redundancies of the ASIC design is effectively reduced; and the design redundancy degree is further reduced.

Description

technical field [0001] The invention relates to the technical field of chip design, in particular to an optimization method and system for netlist logic redundancy in ASIC design. Background technique [0002] At present, in the logical design process of conventional ASIC (Application Specific Integrated Circuits, Application Specific Integrated Circuits) chips, code modification or version update usually produces certain logical redundancy. Although this kind of logical redundancy will not have a bad impact on chip functions, it also has many adverse effects such as occupying chip resources and increasing chip power consumption. Therefore, for chips that currently pursue extremely low power consumption, reducing ASIC Logic redundancy in design is an important means and necessary link to reduce power consumption. [0003] However, at present, the major EDA tools in the industry are not perfect in optimizing and removing logic redundancy. Among the existing methods for redu...

AI Technical Summary

Problems solved by technology

The whole process is not only time-consuming and labor-intensive, but also the probability of manual modification errors is quite high

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