Decoding method of low-density parity check codes

Abstract

The invention discloses a decoding method of low-density parity check codes. The method includes the following steps that: type analysis is performed on the low-density parity check codes, so that the feature information of the low-density parity check codes can be obtained; the check information and variable information of the low-density parity check codes are stored according to the feature information; a check sub matrix corresponding to the check information is determined through the check information; and decoding of the low-density parity check codes is realized through the check sub matrix and a variable matrix corresponding to the variable information.

Description

technical field [0001] The invention relates to the technical field of communication, in particular to a decoding method of a low density parity check code. Background technique [0002] In information warfare, the tactical data link is one of the key elements for combat troops to obtain battlefield information advantages, improve the rapid response capability and collaborative combat capability of combat platforms, and realize command automation. With the continuous improvement of modern weaponry and combat systems, especially the need for large-capacity tactical information and multi-weapon platform coordinated operations, higher requirements are placed on the tactical performance of tactical data links. On the one hand, a large number of radar, communication and electronic interference equipment are equipped on ships, aircraft and other weapons, and the electromagnetic environment of the battlefield is becoming more and more complex, which requires the tactical data link ...

AI Technical Summary

Problems solved by technology

In the existing method of decoding LDPC codes using Field Programmable Gate Array (Field-Programmable GateArray, FPGA), the input and output control of data is realized by circular shifting of registers. This method requires a configurable circular shifting The switching network is used for dynamic sorting of data. The configurable cyclic shift switching network needs to occupy additional logic resources, and the initial message of the channel needs to be interleaved before being sent to the decoder, and the decoded output bits must be deinterleaved to restore the original To send a bit sequence, the introduction of an interleaver not only consumes additional logic resources, but also increases the decoding delay. At the same time, this method is a challenge for the realization of irregular LDPC codes

At the same time, in the existing partial parallel decoding method, the parallelism of the LDPC code decoding algorithm is that each row block of the quasi-cyclic parity check matrix in the decoder structure corresponds to a check node processing module, and each column block corresponds to a variable Node processing module, decoding parallelism is relatively fixed

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