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Method of Prolonging Data Retention Time in Hybrid Memory

A hybrid memory and data retention technology, applied in the memory field, can solve problems such as crashes and user data loss, and achieve the effects of extending service life, data retention time, and data retention time

Active Publication Date: 2018-08-28
SHANGHAI XINCHU INTEGRATED CIRCUIT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the system reads data from the storage array of MLC, TLC, 3D-NAND in NAND hybrid memory or NAND memory chips in new hybrid memory, if the number of data errors has exceeded the maximum number of bits that can be corrected by the detection and correction module number, the system may crash due to this wrong data, causing the user to lose some important data

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  • Method of Prolonging Data Retention Time in Hybrid Memory
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  • Method of Prolonging Data Retention Time in Hybrid Memory

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Experimental program
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Embodiment 1

[0032] Figure 5 It is a schematic structural diagram of Embodiment 1 of the hybrid solid-state memory of the present invention, such as Figure 5 As shown, this embodiment now proposes a method for prolonging the data retention time in the hybrid memory, for example, there are N levels of different types of memory chips in the hybrid solid-state memory, from the 0th level to the N-1th level, the number of memory chips The data retention time decreases gradually, and that is to say, the data retention time of the first level is the longest, and the data retention time of the N-1th level is the worst. The different types of memory chips can be NAND flash memory chips, such as single-layer cell NAND chips (SLC), double-layer cell NAND chips (MLC), triple-layer cell NAND chips (TLC), or 3D-NAND type The chips and the like may also be new memory chips, such as phase change memory (PCM), magnetic random access memory (MRAM), resistive memory (RRAM), ferroelectric memory (FeRAM) an...

Embodiment 2

[0036] Figure 6 It is a schematic structural diagram of Embodiment 2 of a hybrid memory with multi-layer chips in the present invention; for the convenience of description, this embodiment will specifically assign values ​​as follows, in a NAND hybrid memory such as Figure 6 As shown, NAND hybrid memory contains SLC, MLC, TLC and 3D-NAND four-level structure. Suppose the data retention time of SLC is H_S, the data retention time of MLC is H_M, the data retention time of TLC is H_T, the data retention time of 3D-NAND is H_D, and the data retention time of the four kinds of memories is H_S>H_M>H_T> H_D. Assuming that the system reads 512 bits of data from the storage array of the NAND hybrid memory each time, the maximum number of bits that can be detected and corrected by the detection and correction module is 10 bits and 8 bits respectively, and the system sets the early warning value of the detection and correction module to be 6 digits. When the system reads data from 3...

Embodiment 3

[0038] Figure 7 It is a structural schematic diagram of Embodiment 3 of the novel memory chip and the NAND memory chip of the present invention, such as Figure 7 As shown, in the new hybrid memory, it is assumed that the data retention time of the new memory chip is H_N, and the data retention time of the NAND memory chip is H_D, and the data retention time of the two types of memory is H_N>H_D. Assuming that the system reads 256 bits of data from the storage array of the new hybrid memory each time, the maximum number of bits that can be detected and corrected by the detection and correction module is 8 bits and 7 bits respectively, and the system sets the early warning value of the detection and correction module to be 5 digits. According to the active detection method proposed by the present invention, when the system is in an idle state or within the T time set by the system, the detection and correction module detects that there are 5 or more bits in the 256-bit data G...

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Abstract

The invention relates to the field of memories and particularly relates to a method for prolonging retention time of data in a mixing memory. The method for prolonging the retention time of the data in the mixing memory comprises the following steps: setting an early warning value; and when an error bit of the data read from a lower-grade memory of the mixing memory reaches the early warning value, storing the data or whole page data of the data or whole block data of the data into an upper-grade memory, wherein the data retention time of the upper-grade memory is longer than that of the lower-grade memory.

Description

technical field [0001] The invention relates to the field of memory, in particular to a method for extending data retention time in a hybrid memory. Background technique [0002] figure 1 It is a structural schematic diagram of a NAND hybrid memory in the prior art. The NAND hybrid memory mixed with NAND flash memory as a storage medium is as follows: figure 1 As shown, the first level is a single-layer cell type NAND chip (SLC), the second level is a double-layer cell type NAND chip (MLC), the third level is a three-layer cell type NAND chip (TLC), and so on and the last level 3D-NAND type chips, these types of chips are controlled by the storage logic controller to read and write operations and execute some specific algorithms, such as data management, wear leveling, etc. figure 2 The advantages and disadvantages of these types of memory are compared. [0003] Such as figure 2 As shown, in the NAND hybrid memory, the four chips are SLC, MLC, TLC, 3D-NAND in the order...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F3/06
Inventor 景蔚亮陈邦明
Owner SHANGHAI XINCHU INTEGRATED CIRCUIT