Adjusting and optimizing method utilizing PID to achieve fluctuations of CPU and internal storage VR output voltage

An output voltage and memory technology, applied in the field of general server power supply, can solve the problems of system downtime and large voltage fluctuation, and achieve the effect of improving product quality, ensuring power supply stability, and improving debugging efficiency

Inactive Publication Date: 2016-02-03
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
View PDF5 Cites 4 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This will lead to: the output voltage of the CPU and memory VR on the main board of the server, in some user applications, there will be large voltage fluctuations
Once the voltage fluctuation exceeds SPEC, it will cause system downtime.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Adjusting and optimizing method utilizing PID to achieve fluctuations of CPU and internal storage VR output voltage
  • Adjusting and optimizing method utilizing PID to achieve fluctuations of CPU and internal storage VR output voltage

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0029] An optimization method that uses PID to realize the output voltage fluctuation of CPU and memory VR. By adjusting the PID parameters in the main chip of CPU and memory VR, combined with the measurement of VR Bode diagram, the optimal PID parameters are obtained to achieve The adjustment of the CPU and memory VR output voltage keeps the CPU and memory VR output voltage within a small fluctuation range under various load conditions, enhancing the power supply stability of the server system.

Embodiment 2

[0031] On the basis of embodiment 1, the implementation steps of the method described in this embodiment are as follows:

[0032] 1) if figure 2 As shown, build a debugging platform: select the mainboard of the server to be debugged, connect the signal probe of the frequency response analyzer to the 10ohm resistor of the feedback terminal of the CPU or memory VR to be tested (the 10ohm resistor has been reserved for debugging when the motherboard is designed , after mass production, the resistor will be removed);

[0033] 2) Connect the frequency response analyzer to the PC computer with a USB-GPIB conversion cable;

[0034] 3) Connect the digital VR debugging tool to the I2C interface of the motherboard, and plug the other end of the tool into the USB interface of the PC;

[0035] 3) After the debugging platform is built, open the installed digital VR debugging software (such as Infineon's Powercode4.3) on the PC. At the same time, open the installed Bode plot (ie: bodepl...

Embodiment 3

[0043] On the basis of Embodiment 2, this embodiment solidifies the obtained optimal PID in the digital VR chip, which can realize the optimization of VR output voltage fluctuation, and realize the output voltage of CPU and memory VR under all user loads , the voltage fluctuations are within the safe voltage range, ensuring the stability of the power supply of the server system.

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses an adjusting and optimizing method utilizing PID to achieve fluctuations of CPU and internal storage VR output voltage. CPU and internal storage VR output voltage can be adjusted via adjustments of parameters of PID in the CPU and an internal storage main chip, so the CPU and internal storage VR output voltage can be always remained in a small fluctuant range under various load conditions; and server system power supplying stability can be enhanced. R&D engineers can adjust fluctuations of CPU and internal storage VR output voltage without welding an element component via a solder and only requiring PID parameter adjustments on a software interface of a digital power supply, so debugging efficiency of the engineers can be improved and R&D period is shortened; PID adjustments and VR bode diagram measurements are combined to achieve optimized PID parameters, so stability of the CPU and internal storage VR output voltage of the server in all user application scenes can be guaranteed and product quality is improved.

Description

technical field [0001] The invention relates to the technical field of general server power supply, in particular to a method for optimizing the output voltage fluctuation of CPU and memory VR by using PID, and a method for ensuring the stability of the output voltage of mainboard CPU and memory VR. Background technique [0002] In a server system, the functional units with the fastest load changes are mainly concentrated in the CPU and memory. The current of the CPU and memory loads changes greatly, and the frequency of the change is very complicated, which leads to complex fluctuations in the VR power supply voltage of the CPU and memory. The fluctuations of these two VR voltages often have a fatal impact on the stability of the server system, causing blue screens and downtime failures in the user system. [0003] General-purpose servers have particularly stringent requirements on system stability. Because the general-purpose server is oriented to a large number of custo...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G06F11/22
Inventor 宋晓锋罗嗣恒
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products