A Shared Memory Interface for Multicore Parallel Video Encoding and Decoding

Abstract

The invention provides a shared memory interface used for multi-core parallel video coding and decoding. The shared memory interface comprises a data structure and an establishing and using method thereof; and the establishing method comprises the steps of (11) dividing image data to m cores according to an equal division principle; (12) opening up a section of continuous memory space in a shared memory by the m cores and sending a head address of a data buffer region returned by a system to an appointed core A through an inter-core message; (13) opening up a section of continuous memory space in a private memory by all the cores and starting setting from the head address of the data buffer region returned by the system; (14) starting setting the p-1 class table content of all the p-dimension arrays of the image data sequentially from the head address of the buffer region sent from each core by the core A; and (15) sending the p-1 class table content of all the p-dimension arrays of the image data to all the cores by means of interclass broadcasting and through an inter-core high-speed interconnection network by the core A. The shared memory interface used for multi-core parallel video coding and decoding has the advantages of allocating data buffer to the multiple cores correspondingly after tasks are allocated to the multiple cores, realizing balance and increasing shared data access efficiency remarkably.

Description

technical field [0001] The invention relates to the technical field of video coding, in particular to a multi-core parallel video coding and decoding method using a multi-core digital signal processor DSP chip to complete high-definition video coding, decoding and transmission, and an optimization measure for caching during multi-core parallelism. Background technique [0002] In the 1980s, the mutual penetration and integration of 3C (Computers, Communications, Consumer Electronics) gave birth to multimedia technology and promoted the rapid development and popularization of multimedia technology. Video coding is a key technology in multimedia technology. In recent years, the clarity of transmitted video has been continuously improved, and at the same time, video coding standards have been frequently updated, and new content has continued to emerge. In 2002, CIF H.263 still occupied the mainstream in conference TV equipment. 720P H.264 appeared in 2005. By 2009, 1080P con...

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Problems solved by technology

[0021] The technical problem to be solved by the present invention is the multi-core parallel cache imbalance problem encountered in the six core H.264 parallel decoding on Tile64 in Document 2. The phenomenon is that the parallel decoding speed of six cores is more than 2 times slower than that of a single core. The reason is that the traditional integrated shared data is still used when the distributed cache of Tile64 cannot cache data for multiple cores in parallel. The shared data accessed by the five cores #1 to 5 is all opened up by core #0, and core #0 It is the mother core and is cached in the secondary cache of core #0. Each access requires data packets to be transmitted between cores, even repeated accesses require repeated transmission of data packets, and the access efficiency is very low; at this time, the internal secondary cache of core #0 The cache is actually used as a cache for 6 cores, and the capacity of a mere 64K bytes is simply not enough for the total data throughput of 6 cores' high-speed processing, so the chances of cache misses also increase sharply.

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