Unlock instant, AI-driven research and patent intelligence for your innovation.

Test Methods for Wafer Level Chip Scale Packages

A chip size packaging and testing method technology, applied in semiconductor/solid-state device testing/measurement, electrical measurement, measurement device, etc., can solve problems such as process blocking, and achieve the effect of solving process blocking

Active Publication Date: 2017-03-08
MEMSIC SEMICON WUXI
View PDF9 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] One of the technical problems solved by the present invention is to provide a method for testing wafer-level chip-scale packaged devices, which can solve the problem of flow blockage in the prior art

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Test Methods for Wafer Level Chip Scale Packages
  • Test Methods for Wafer Level Chip Scale Packages
  • Test Methods for Wafer Level Chip Scale Packages

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0022] As shown in the accompanying drawings, specific embodiments have been described in detail herein, and the description has taken numerous details to provide a thorough understanding of the invention. Various changes can be made within the scope of the technical gist of the present invention as long as the relevant general knowledge is acquired in the technical field to which the present invention pertains. The scope of protection of the present invention is not limited to the embodiments, but all equivalent modifications or changes made according to the disclosure of the present invention should be included in the scope of protection described in the claims.

[0023] The test method of traditional WLSCSP package comprises the following steps: 1) the whole wafer is diced and divided into individual chips; 2) the single chip is loaded into the carrier; 3) the chip is tested in parallel; 4) the chip is loaded into the reel with packaging.

[0024] figure 1 A typical wafer...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a test method for wafer-level chip size packaging, which includes: dicing and cutting a wafer of wafer-level chip size packaging into a plurality of wafer strips, each wafer strip including multiple unscribed chip-scale packaged devices; each wafer strip is placed on a corresponding strip carrier; each chip size in the wafer strip placed on the strip carrier is tested using the test equipment testing the packaged devices; and dicing the tested wafer strips into individual chip-sized packaged devices. Since instead of loading many divided chips into the socket one by one, a limited number of wafer strips are placed in the strip carrier, so that the flow blockage is avoided.

Description

technical field [0001] The invention relates to the testing of wafer-level chip size packaging devices, in particular to a testing method for wafer-level chip size packaging of a micro-electro-mechanical system (micro-electro-mechanical-system, MEMS). Background technique [0002] Wafer-level chip scale packaging (WLCSP for short) is widely used in the MEMS industry. Since WLCSP does not require lead frames and wire bonding, the low cost of packaging makes it popular. Especially in the field of consumer electronics, MEMS-based WLCSP products will replace sensors packaged in traditional processes. Therefore, an accurate and efficient method is needed to test MEMS-based WLCSP products. [0003] In order to achieve high-efficiency testing, traditionally packaged sensors are usually placed one by one in complex and expensive carriers or test sockets for parallel testing. Using a pick and place machine to process a single packaged sensor may cause process blockage, resulting i...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): B81C99/00
CPCB81C99/0045B81C1/00904H01L22/14H01L23/544H01L21/6835H01L2223/54433H01L2223/54453G01R31/2891G01R31/2893G01R31/2898B81C99/004H01L21/6836H01L22/20H01L23/3114H01L2221/68327B81C1/00896H01L21/78H01L22/32
Inventor 赵阳文彪蒋乐跃刘海东程安儒李斌
Owner MEMSIC SEMICON WUXI