Control circuit of SRAM array and SRAM

Abstract

The invention discloses a control circuit of an SRAM array and an SRAM. The control circuit comprises a first PMOS transistor, a conduction control unit and at least one pull-down MOS transistor, wherein the source of the first PMOS transistor is suitable for inputting a first voltage; the drains of the pull-down MOS transistors are all connected with the drain of the first PMOS transistor, the sources of the pull-down MOS transistors are all suitable for inputting second voltages, and the voltage value of each second voltage is lower than the voltage value of the first voltage; and the conduction control unit is suitable for controlling all or part of the pull-down MOS transistors to be in conduction states within a predetermined time before the SRAM array enters a working state and performs a write operation.

Description

technical field [0001] The invention relates to the field of memory, in particular to a control circuit of an SRAM memory array and an SRAM memory. Background technique [0002] Static Random Access Memory (SRAM) has the advantageous feature of retaining data without needing to be updated. figure 1 It is a circuit diagram of an existing storage array power consumption control. The second PMOS is connected to the gate and drain of P2, which is equivalent to the function of a diode. When both the Sleep signal and the ShutDown signal are logic 0, both the first PMOS transistor P1 and the third PMOS transistor P3 are in the conduction state, and the conduction of the first PMOS transistor P1 can make the voltage at point VA equal to or very close to the power supply voltage VDD , at this time the storage array 101 enters a working state, and can perform read and write operations. [0003] When the Sleep signal is logic 1 and the ShutDown signal is logic 0, the first PMOS tran...

AI Technical Summary

Problems solved by technology

[0008] The problem solved by the present invention is that the cost and difficulty of performing the write operation of the existing SRAM storage array are high

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