A low-power RFID tag pie decoding method and a decoder applying the method

Abstract

The invention relates to a low-power-consumption RFID-tag-based PIE decoding method. The method comprises: (1), a sign bit sequence is decoded; to be specific, a time length standard value for comparison and determination is constructed, a series of processing is carried out on a lead code part of PIE coding, counting is carried out on TART and RTcal by using a system clock period, and the counting value is divided by three to obtain a processing result marked as NP; and (2), counting is carried out on lengths of follow-up PIE symbols; if the length of the symbol behind the RTcal is larger than the twofold NP, determination of TRcal is made; if the length of the symbol is larger than or equal to the NP, the logic is determined to be ''1''; if the length of the symbol is smaller than the NP, the logic is determined to be ''0''; and the follow-up symbol length is equal to the sum of lengths of a continuous high level and low level part; and if the high level length is larger than the fourfold NP, PIE coding is determined to be ended. According to the invention, the system clock frequency can be reduced, so that the power consumption is obviously reduced and the receiving sensitivity is improved.

Description

technical field [0001] The invention belongs to the technical field of power metering, and relates to an integrated circuit, in particular to a PIE decoding method for a low-power RFID tag and a decoder applying the method. Background technique [0002] At present, there are two main schemes for UHF RFID tags to decode the PIE format encoding symbols of the 6C protocol. [0003] The first solution is to count the entire length of RTCAL (including high level and low level), and calculate the intermediate value pivot=RTcal / 2. Afterwards, count the entire length of the subsequent symbol (including high level and low level), and compare it with the pivot to determine whether the symbol is Data-0 or Data-1. This solution has high requirements for the system clock system, resulting in high overall power consumption; [0004] The second scheme is to count the entire length of RTCAL (including high level and low level), and can calculate (RTCAL / 2-PW ) to get the standard value 1....

AI Technical Summary

Problems solved by technology

This scheme still has high requirements for the system clock system. Although the counting is stopped at the low level stage of the symbol, which reduces the circuit consumption, the reduction of power consumption is related to the communication configuration (such as the ratio of Data-1 to Tari), and the Data-1 in the data. The number of 1 is related. When Data-1 changes from 1.5Tari to 2Tari, or when the number of logic "1" in the transmission information is large, because the proportion of low level becomes smaller, the proportion and effect of power consumption reduction are very different. Big

On the other hand, the premise of this scheme is that all PIE symbols received in an inventory cycle have the same shape and duty cycle, otherwise the possibility of misjudgment will be greatly increased, which has very high requirements for the front-end analog circuit. Increased the area and power consumption of the analog circuit

[0005] Therefore, this article focuses on the need to solve the problem of high system clock frequency during the PIE decoding process, resulting in high chip power consumption and low label sensitivity

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