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Lithography process and system with enhanced overlay quality

A lithography system and process technology, applied in the field of lithography process and system, can solve the problems of increasing the complexity of processing and manufacturing IC

Active Publication Date: 2019-02-05
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] This scaling down process also increases the complexity of processing and manufacturing ICs, and, to achieve these advances, similar developments in IC processing and manufacturing are required
For example, reducing overlay errors induced in lithographic patterning and improving lithographic techniques are more challenging

Method used

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  • Lithography process and system with enhanced overlay quality
  • Lithography process and system with enhanced overlay quality
  • Lithography process and system with enhanced overlay quality

Examples

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Embodiment Construction

[0033] The following disclosure provides many different embodiments or examples for implementing different features of the presented subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which the first component and the second component may be formed in direct contact. An embodiment in which an additional part is formed so that the first part and the second part may not be in direct contact. In addition, the present invention may repeat reference numerals and / or letters in various instances. This repetition is for the sake of simplicity and clarity and does not in itself indicate a relations...

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PUM

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Abstract

The present disclosure provides a method. The method includes forming a resist layer on a patterned substrate; collecting first overlay data from the patterned substrate; determining an overlay compensation based on mapping of second overlay data from an integrated circuit (IC) pattern to the first overlay data from the patterned substrate; performing a compensation process to a lithography system according to the overlay compensation; and thereafter performing a lithography exposing process to the resist layer by the lithography system, thereby imaging the IC pattern to the resist layer.

Description

technical field [0001] The present invention relates to photolithographic processes and systems with enhanced coverage quality. Background technique [0002] The semiconductor integrated circuit (IC) industry has experienced exponential development. Technological advances in IC materials and design have produced generations of ICs, with each generation of ICs having smaller and more complex circuits than the previous generation of ICs. In the course of IC evolution, functional density (ie, the number of interconnected devices per chip area) has generally increased while geometry size (ie, the smallest component (or line) that can be made using a fabrication process) has decreased. Often this scaling down process benefits by increasing production efficiency and reducing associated costs. [0003] This scaling down process also increases the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are required in order to ac...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G03F7/20G03F9/00
CPCG03F7/70633G03F7/70258G03F7/705
Inventor 洪继正林纬良严永松陈俊光刘如淦高蔡胜傅中其董明森梁辅杰陈立锐陈孟伟陈桂顺
Owner TAIWAN SEMICON MFG CO LTD