Three-dimensional semiconductor device and manufacturing method thereof

Abstract

The invention discloses a three-dimensional semiconductor device, which comprises multiple storage units. Each storage unit comprises a channel layer stack, multiple insulated layers, multiple pairs, a tunneling layer, a drain and a source, wherein the channel layer stack is distributed along the direction vertical to the surface of a substrate; the multiple insulated layers are alternately stacked along the side wall of the channel layer stack; the multiple pairs are formed by floating gates and control gates and horizontally and adjacently located between adjacent insulated layers, and at least one blocking layer exists between the floating gate and the control gate; the tunneling layer is located between the floating gate and the side wall of the channel layer stack; the drain is located at the top of the channel layer stack; the source is located on the substrate between adjacent two storage units of the multiple storage units; and the floating gates and the control gates are mutually matched to form a bent interface. According to the three-dimensional semiconductor device and the manufacturing method thereof, the control gates and the floating gates can be mutually engaged in the same horizontal level, the coupling coefficient from the control gates to the floating gates is effectively improved, coupling between vertical string units is reduced, and device reliability is improved.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a three-dimensional semiconductor storage device and a manufacturing method thereof. Background technique [0002] In order to improve the density of memory devices, the industry has made extensive efforts to develop methods of reducing the size of two-dimensionally arranged memory cells. As the size of memory cells in two-dimensional (2D) memory devices continues to shrink, signal collisions and interference can increase significantly, making it difficult to perform multi-level cell (MLC) operations. In order to overcome the limitations of 2D memory devices, the industry has developed memory devices with a three-dimensional (3D) structure to increase integration density by three-dimensionally arranging memory cells on a substrate. [0003] Specifically, a multi-layer stacked structure (for example, multiple ONO structures alternating with oxides and n...

AI Technical Summary

Problems solved by technology

In 3D NAND, the existing structure makes it difficult to increase the coupling coefficient from the control gate to the floating gate, which increases the erasing voltage and degrades the retention characteristics and durability of the storage device.

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