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biased electrostatic discharge (ESD) circuit and method reducing capacitance of ESD circuit

An electrostatic discharge and circuit technology, applied in the field of electrostatic discharge protection, can solve problems such as damage to electronic devices

Active Publication Date: 2016-03-09
FAIRCHILD SEMICON SUZHOU +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In some instances, ESD currents can be large enough to damage electronic devices

Method used

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  • biased electrostatic discharge (ESD) circuit and method reducing capacitance of ESD circuit
  • biased electrostatic discharge (ESD) circuit and method reducing capacitance of ESD circuit
  • biased electrostatic discharge (ESD) circuit and method reducing capacitance of ESD circuit

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Embodiment Construction

[0010] The present inventors have also recognized, among other things, that a bias voltage can be applied to an electrostatic discharge (ESD) structure, such as a well region or a gate in an ESD structure, to reduce the capacitance of the ESD structure, while other ESD structures Parameters vary little to no.

[0011] Figure 1-Figure 3 An exemplary biased electrostatic discharge (ESD) circuit configured to provide an ESD path to ground through an ESD device 1 such as an n-type metal oxide semiconductor (NMOS) transistor is generally shown, the circuit having a gate terminal 2 , drain terminal 3, source terminal 4, and body terminal 5 (eg, p-epi / p body terminal). Figure 1-Figure 3 The bias ESD circuit uses a negative voltage applied (e.g., externally) to the body terminals (e.g., p-epi / p body) of the ESD device to reduce the source / drain capacitance of the ESD device (e.g., n+ source / drain electrode-to-body capacitance), thereby reverse-biasing the well region to the drain ca...

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Abstract

This document discusses, among other things, a biased electrostatic discharge (ESD) circuit and a method reducing capacitance of the ESD circuit. The ESD circuit is configured to reduce capacitance of an ESD structure with little to no change in other ESD structure parameters. A bulk terminal of an ESD device can be negative biased to reduce a drain terminal to source terminal capacitance of the ESD device. A charge pump can be configured to provide a negative bias to the bulk terminal of the ESD device. In certain examples, the gate terminal of the ESD device can be coupled to the source terminal of the ESD device, such as through a resistor, and the source terminal can be coupled to ground.

Description

technical field [0001] The present application relates to electrostatic discharge (ESD) protection, and more particularly, to methods of biasing electrostatic discharge (ESD) circuits and reducing the capacitance of electrostatic discharge circuits. Background technique [0002] Electrostatic discharge (ESD) is the sudden flow of electrical charge between objects. In some instances, ESD currents can be large enough to damage electronic devices. To protect electronic devices from ESD events, various ESD protection circuits have been designed to shunt the ESD current to ground. Contents of the invention [0003] This document discusses, among other things, biased electrostatic discharge (ESD) circuits configured to reduce the capacitance of an ESD structure with little to no change in other ESD structure parameters and methods thereof. The body terminal of the ESD device can be negatively biased to reduce the drain terminal to source terminal capacitance of the ESD device....

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/0175H10N97/00
CPCH02H9/046H01L27/0266
Inventor 科奈斯·P·斯诺登T·康李永亮
Owner FAIRCHILD SEMICON SUZHOU
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