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Satellite link time delay simulation device based on field programmable gate array (FPGA)

A satellite link and simulation device technology, applied in the field of satellite communication, can solve the problems of lack of programmable expansion capability, inability to provide high-precision, high-performance time-delay simulation capability, and high price, so as to achieve flexible operation, high precision, low cost effect

Active Publication Date: 2016-03-09
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] (1) Although the hardware delay simulator based on a dedicated ASIC design has high precision and strong functions, it is too expensive and lacks programmable expansion capabilities
[0013] (2) Although the delay simulator based on software has great advantages in flexibility, it cannot provide high-precision and high-performance delay simulation capabilities

Method used

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  • Satellite link time delay simulation device based on field programmable gate array (FPGA)
  • Satellite link time delay simulation device based on field programmable gate array (FPGA)
  • Satellite link time delay simulation device based on field programmable gate array (FPGA)

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Embodiment Construction

[0029] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0030] Such as figure 1 Shown, FPGA-based satellite link delay simulation device of the present invention comprises:

[0031] The IP message discrimination module is used to receive the input message through the input control unit and output the IP message;

[0032] The delay control module is used to receive the IP message sent by the IP message discrimination module, and send it out after delay processing; the simulation operation object of the delay control module is the link transmission delay of multiple consecutive Ethernet IP data messages. Time. This module can not only accurately simulate the fixed delay of the satellite link, but also effectively simulate the variable delay in the link. The internal analog parameters of the module will be set by the user through the configuration bus.

[0033] The output polling module i...

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Abstract

The invention discloses a satellite link time delay simulation device based on a field programmable gate array (FPGA). The satellite link time delay simulation device comprises the components of an IP message discrimination module which is used for receiving an input message through an input control unit and outputting an IP message; a time delay control module which is used for receiving the IP message that is transmitted from the IP message discrimination module and transmitting out after time delaying processing; and an output polling module which is used for cooperating with the time delay control module and an output control module for finishing message outputting. The satellite link time delay simulation device based on the FPGA has advantages of high precision, flexible operation, low cost, etc.

Description

technical field [0001] The invention mainly relates to the field of satellite communication, in particular to an FPGA-based satellite link delay simulation device. Background technique [0002] The satellite link is the basis of space-ground integrated network communication, and it is also a key factor affecting the performance of space-space-ground integrated network. The testing, verification and evaluation of air-space-ground integrated network urgently needs to establish a real and credible simulation experiment environment. Link simulation technology is one of the key technologies that must be solved to build such an environment. Therefore, it is of great significance to carry out the development of satellite link simulator. [0003] The satellite link has distinctive characteristics such as long delay, high bit error, and asymmetry. The delay simulation is one of the important functions of the satellite link simulator. In the space environment, the transmission dista...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04B7/185H04B17/391
CPCH04B7/1851
Inventor 赵宝康毛席龙苏金树赵国鸿陈一骄崔向东吕高锋李韬韩彪杨惠保金帧王会强
Owner NAT UNIV OF DEFENSE TECH