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nmos transistors and methods of forming them

A technology of transistors and semiconductors, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of NMOS transistor performance to be improved, and achieve the effect of preventing void defects

Active Publication Date: 2018-09-07
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] However, the performance of NMOS transistors formed by existing technologies still needs to be improved

Method used

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  • nmos transistors and methods of forming them
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  • nmos transistors and methods of forming them

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Experimental program
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Embodiment Construction

[0037] As mentioned in the background art, the performance of the NMOS transistors formed in the prior art still needs to be improved. It is easy to generate void defect 109 in the gate electrode. For details, please refer to image 3 .

[0038] For research findings, please refer to figure 2 and image 3 In the manufacturing process of the NMOS transistor, after removing the dummy gate to form the second groove 105, the sidewalls 103 on both sides tend to incline toward the direction of the second groove 105, so that the width of the opening of the second groove 105 will be reduced. Small (the width of the upper part of the second groove 105 is smaller than the width of the lower part), so when forming a metal layer filling the second groove 105, the metal material is easy to block the opening of the second groove 105, so that the second groove 105 The void defect 109 is likely to be generated in the metal gate electrode 107 formed in . Further studies have found that th...

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Abstract

The invention provides a negative metal oxide transistor (NMOS) transistor and a forming method thereof, wherein the forming method of the NMOS transistor comprises the steps of providing a semiconductor substrate on which a dummy gate is formed, wherein a sidewall is formed on the side wall of the dummy gate, and a carbon silicon source region and a carbon silicon drain region are formed in the semiconductor substrate at the side of the dummy gate and the side of the sidewall; forming a dielectric layer on the semiconductor substrate, wherein the surface of the dielectric layer is level with the surface of the dummy gate, and performing back etching for eliminating partial-thickness dummy gate, and exposing partial surface of the sidewall of the side wall; etching for eliminating partial-height sidewall; eliminating the rest dummy gate and forming a T-shaped recessed trough, and the T-shaped recessed trough is exposed from the surface of the semiconductor substrate; and forming a metal gate which fills the T-shaped recessed trough. According to the forming method of the invention, the opening width of the formed recessed trough is increased and a defect in the metal gate in formation of the metal gate is prevented.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to an NMDOS transistor and a forming method thereof. Background technique [0002] As the feature size of semiconductor devices becomes smaller and smaller, the area occupied by the corresponding core devices is also reduced accordingly, resulting in a substantial increase in energy density per unit area, more prominent leakage problems, and increased power consumption. Therefore, in the process below 45 nanometers, the traditional process of using silicon dioxide as a gate dielectric layer has encountered a bottleneck and cannot meet the process requirements of semiconductor devices; in order to solve the above bottleneck, a high dielectric constant (high k: k value is greater than or equal to 3.5) the dielectric material is used as the gate dielectric layer, and then a gate made of metal is formed to reduce leakage, so that power consumption is well controlled. [0003]...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L29/78
Inventor 张海洋郑喆
Owner SEMICON MFG INT (SHANGHAI) CORP