Semiconductor device manufacturing method

Abstract

The invention relates to a manufacture method of a semiconductor device. The method comprises that multiple fins which extend along the first direction are formed on a substrate; a pseudo-grid stack structure which extends along the second direction is formed on the fins; grid sidewalls are formed at the two sides along the first direction of the pseudo grid stack structure; lightly-doped ion implantation is implemented by taking the grid sidewalls as the mask, a source-drain extension area is formed between the fins, at the two sides along the first direction, of the grid sidewalls, a vertical inclined angle is formed between the ion implantation direction and the vertical direction, and a horizontal inclined angle is formed between the ion implantation direction and the first direction; the pseudo grid stack structure is removed to form a grid channel; and a grid stack structure is formed in the grid channel. According to the manufacture method, the horizontal included angle between the inclined ion implantation direction and the fin structure is adjusted to effectively control the uniformity and horizontal junction depth of the LDD / SDE structure, and improve the stability of the device.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor device, in particular to a method for manufacturing a three-dimensional multi-gate FinFET with a source-drain extension region with a uniform lateral junction depth. Background technique [0002] In the current sub-20nm technology, the three-dimensional multi-gate device (FinFET or Tri-gate) is the main device structure, which enhances the gate control capability and suppresses leakage and short channel effects. [0003] For example, compared with traditional single-gate bulk Si or SOI MOSFETs, MOSFETs with double-gate SOI structures can suppress short-channel effects (SCE) and drain-induced barrier lowering (DIBL) effects, have lower junction capacitance, and can To achieve light channel doping, the threshold voltage can be adjusted by setting the work function of the metal gate, which can obtain about 2 times the driving current and reduce the requirements for the effective gate oxid...

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Problems solved by technology

However, as the size of the device continues to shrink, the gate sidewall continues to thin and the length of the fin along the channel direction also decreases. It is difficult to obtain a uniformly distributed LDD / SDE structure only by controlling the vertical tilt angle, and it is also difficult to reasonably adjust the lateral direction. The junction depth is required to obtain the required channel region and source-drain region interface characteristics. Different batches of devices have performance differences due to process parameter drift, which reduces the stability of the entire batch of products.

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