Array substrate, display panel and display device

Abstract

The invention discloses an array substrate, a display panel and a display device. The array substrate comprises an underlying substrate, and data lines and thin-film transistors which are arranged on the underlying substrate. The source electrode of each thin-film transistor comprises a first child source electrode and a second child source electrode. The first child source electrode and the second child source electrode are respectively connected with the data lines. The drain electrode of each thin-film transistor comprises a first child drain electrode which is arranged between the first child source electrode and the second child source electrode. Effective channel regions are respectively formed by the first child source electrode and the second child source electrode and the first child drain electrode respectively. The first child source electrode and the second child source electrode are mutually parallel and are respectively connected with the data lines, i.e. the first child source electrode and the second child source electrode are not intersected so that overlapping area of the source electrode and the gate electrode can be reduced, overlapping capacitance can be reduced and thus load can be reduced; besides, influence of capacitance on chargeability is far greater than influence of resistance so that linewidth can be properly reduced, aperture ratio can be enhanced and chargeability can be ensured by using the array substrate.

Description

technical field [0001] The invention relates to the field of display technology, in particular to an array substrate, a display panel and a display device. Background technique [0002] At present, large-size Ultra High Definition Television (UHD for short) products are the key development direction of TV products, and its resolution can reach 3840x2160, especially for Gate Driven Array (GOA) UHD TV products. However, due to the short charging time of UHD GOA products and the limitation of GOA drive capability, insufficient charging is a major problem. [0003] In order to meet the charging rate, the charging rate is generally met by increasing the width-to-length ratio of the thin-film transistor (Thin-film Transistor, TFT for short), increasing the line width (such as the width of the data line, the width of the gate), thereby reducing the resistance, etc. Require. However, the TFT aspect ratio and line width will further reduce the original small pixel aperture ratio, t...

AI Technical Summary

Problems solved by technology

However, due to the short charging time of UHDGOA products and the limitation of GOA driving capability, insufficient charging is a major problem.

However, the TFT aspect ratio and line width will further reduce the small pixel aperture ratio, which will affect the transmittance of the panel and increase the power consumption of the backlight.

[0004] Generally, large-size ultra-high-definition display products often use Single Slit Mask (SSM) technology or Modified Single Slit Mask (ModifiedSingleSlitMask, MSM) technology. In the structure of SSMTFT, such as figure 1 As shown, the distance between the gate and the source is very small (about 2um), and the resolution of the exposure machine is generally greater than 2um. The channel area uses grating diffraction to form a semi-transparent area, and after the exposure, development and etching process, a narrow channel is formed. Thus increasing the width-to-length ratio, the area where the entire "U"-shaped channel is located is the effective channel area 01, but the bottom of the SSMTFT channel is prone to poor cr

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