LDPC-CC high speed decoder
An LDPC-CC and decoder technology, applied in the field of LDPC-CC high-speed decoders, can solve the problem that the throughput of the decoder is not satisfactory, the overall throughput of the decoder is difficult to meet high-speed transmission, node message reading Take address conflicts and other issues to achieve the effect of reducing RAM resources, rationally utilizing memory resources, and reducing hardware logic resources
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Embodiment 1
[0053] Assuming that the node parallelism factor is ρ, it means that ρ check node updates are performed at the same time. According to the shift process, at this time, each link should be moved back by ρ positions at each time. folded, folded as Figure 4 shown. At this time, each link is correspondingly folded into ρ branch chains, and the folded branch chains only need to move backward by 1 position at each moment. The branch chain distribution after folding can be determined by the following methods:
[0054] Assuming that a parallel factor of 3 is used, three check nodes are updated at the same time. At this time, the corresponding parity check polynomial is as follows:
[0055] D. 2 (D 6 +D 3 +D 0 )X(D)+D 2 (D 5 +D 2 +D 0 )P(D)=0
[0056] D. 1 (D 6 +D 3 +D 0 )X(D)+D 1 (D 5 +D 2 +D 0 )P(D)=0(5)
[0057] D. 0 (D 6 +D 3 +D 0 )X(D)+D 0 (D 5 +D 2 +D 0 )P(D)=0
[0058] D is the shift delay.
[0059] The parallelism factor is ρ
[0060] Let X=D 3 ...
Embodiment 2
[0072] Embodiment 2, on the basis of the decoder provided in embodiment 1, according to the decoding process, the required message for node update is obtained at the same time, and according to the CNU update formula (1), the key of this unit is to obtain | L(q i'j )|-μ minimum value and sub-minimum value, the process has a large number of logic stages and a long delay, which is the critical path of the processor. If the CNU update is done in one clock cycle, the maximum clock frequency is limited by the critical path and cannot be increased.
[0073] This embodiment proposes a new decoder processing sequence. In this method, the node update unit is set as a multi-cycle path. On the premise of not significantly affecting the throughput of the decoder, the sequence is rearranged so that the two processors can be divided Multiplexing a set of RAM at the same time reduces RAM resources by half.
[0074] Figure 5 Indicates the processor decoding timing. exist Figure 5 Among...
Embodiment 3
[0081] Embodiment 3, the decoding structure adopted in the present embodiment is LDPC-CC high-speed decoder structure, as Image 6 As shown, where CLK_DATA represents the external data input clock and output clock, and CLK_DEC represents the decoding clock. The decoder includes an input buffer module, a message buffer module, a processor module, a verification module, a control module and an output module.
[0082] The input buffer module continuously receives externally input data frames in a ping-pong operation.
[0083] The message buffer module is used to store the channel message output by the last processor or the message passed from the variable node to the check node.
[0084] The verification module judges whether the code word obtained by decoding is correct, and controls whether the decoding is terminated.
[0085] The control module controls signal transmission among various modules.
[0086] The output module outputs the decoded final decision bits.
[0087] T...
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