Semiconductor device with metal gate electrode and manufacturing method for semiconductor device

Abstract

The invention belongs to the technical field of a manufacturing process for a semiconductor integrated circuit, and discloses a semiconductor device with a metal gate electrode. The semiconductor device comprises a substrate, an insulating layer with a groove, and a metal gate electrode structure formed in the groove, wherein the metal gate electrode structure comprises a high K gate dielectric layer, a work function metal layer, a graphene barrier layer, a metal seed crystal layer and gate metal. The invention also discloses a method for manufacturing the semiconductor device with the metal gate electrode. By adoption of the barrier layer made from graphene, the outline appearance of the metal gate groove can be well kept, and the filling property of subsequent gate metal electroplating is not affected; meanwhile, the semiconductor device is excellent in thermal stability and chemical stability; and in addition, the shortcoming of inconsistency of the heights of the metal gates is also avoided, and the yield and the consistency of the device are improved.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuit manufacturing technology, and relates to a semiconductor device with a metal gate electrode and a manufacturing method thereof. Background technique [0002] For more than half a century, integrated circuit (IC) manufacturing technology has been following Moore's Law, achieving a doubling of integration density every 1.5 years. Correspondingly, the size of metal-oxide-semiconductor field effect transistors (MOSFETs) continues to shrink, and The thickness of the gate oxide layer is also continuously reduced. However, entering the 45nm technology node, traditional SiO 2 The thickness of the gate oxide layer is close to the physical limit, and serious reliability problems have occurred. The industry has begun to use SiON instead of SiO 2 , extending the traditional gate structure to the 32nm technology generation. But entering the 28nn technology node, the SiON gate oxide ...

AI Technical Summary

Problems solved by technology

When the gate metal layer, barrier layer and work function metal layer on the surface are removed by the CMP process for a long time, due to the highly selective polishing liquid used for gate metal layer polishing, the CMP process is easily affected by the pattern density effect (loading effect) ,See Figure 2b , compared with the normal metal gate electrode 203, there will be a depression 204 (erosion) in the pattern-intensive area, which will cause the phenomenon of inconsistent height of the metal gate electrode, which will reduce the yield and consistency of the device

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